iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-187/+0
\|
*	simulation: refactoring (move block_instance to iir_values).	Tristan Gingold	2017-11-24	1	-72/+0
\|
*	simulate: add per signal id.	Tristan Gingold	2017-11-16	1	-0/+1
\|
*	simulate: add port map.	Tristan Gingold	2017-11-16	1	-0/+3
\|
*	simulate: reorder block list, support Concurrent_Simple_Signal_Assignment	Tristan Gingold	2017-01-31	1	-0/+4
\|
*	ownership: fix ghdlsimul	Tristan Gingold	2016-12-12	1	-0/+1
\|
*	simulation: reuse Mode_Signal_Type from grt.types.	Tristan Gingold	2016-03-10	1	-14/+11
\|
*	elaboration: use std_time to represent time in signal table.	Tristan Gingold	2016-03-10	1	-1/+2
\|
*	simulation: add block id.	Tristan Gingold	2016-03-10	1	-0/+9
\|
*	simul: preliminary work to support PSL.	Tristan Gingold	2016-02-14	1	-0/+19
\|
*	simul: handle vhdl 2008.	Tristan Gingold	2016-02-06	1	-0/+6
\|
*	simul: use Tables instead of GNAT.Table	Tristan Gingold	2016-01-27	1	-17/+11
\|
*	simul: fix attribute specification, noop type conversion, indiv sig assoc.	Tristan Gingold	2016-01-26	1	-1/+4
\|
*	simul: fix various issues.	Tristan Gingold	2016-01-24	1	-2/+10
\|
*	Adjust simulation after sigptr changes.	Tristan Gingold	2015-12-19	1	-1/+2
\|
*	Simulation: renaming.	Tristan Gingold	2015-01-23	1	-2/+2
\|
*	simulation: rework scope_level.	Tristan Gingold	2015-01-23	1	-1/+4
\|
*	Move translate and simulate.	Tristan Gingold	2014-11-05	1	-0/+209