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* synth: allow constant condition for if-generate statement.Tristan Gingold2020-02-171-0/+1
| | | | For #1076
* synth: add mdff.Tristan Gingold2020-02-174-12/+88
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* netlists-inference: remove useless code.Tristan Gingold2020-02-161-10/+0
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* synthesis: rework memory inference.Tristan Gingold2020-02-163-32/+101
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* synth: handle component with ports in different order.Tristan Gingold2020-02-133-45/+46
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* synth-static_oper: handle more division operands. Fix #1134Tristan Gingold2020-02-121-1/+2
| | | | From donnie-j
* synth: handle null vector for vec-vec concat. Fix #1133Tristan Gingold2020-02-112-6/+12
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* synth-oper: handle add for (natural, unsigned). Fix #1132Tristan Gingold2020-02-111-0/+15
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* netlists-memories: handle split memories. Fix #1127Tristan Gingold2020-02-111-8/+18
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* synth-static_oper: handle xor.Tristan Gingold2020-02-101-0/+11
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* synth-expr: implement value and val attributes. Fix #1130Tristan Gingold2020-02-101-1/+39
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* synth: remove remaining clock edge gates after memories.Tristan Gingold2020-02-102-0/+26
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* netlists-memories: cleanup.Tristan Gingold2020-02-101-319/+1
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* synth: rework (again) memory inference.Tristan Gingold2020-02-108-80/+312
| | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
* synth-inference: minor refactoring.Tristan Gingold2020-02-061-24/+7
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* synth-decls: set a default value to non-assigned signals. Fix #1107Tristan Gingold2020-02-051-1/+3
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* netlists-disp_vhdl: handle 1-bit const_x. For #1107Tristan Gingold2020-02-051-3/+9
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* synth-inference: use the mux output to detect end of walk. Fix #1122Tristan Gingold2020-02-011-1/+8
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* synth-oper: handle std_match for slv. Close #1121Tristan Gingold2020-01-311-1/+2
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* netlists-expands: also handle ror.Tristan Gingold2020-01-301-7/+24
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-305-1/+154
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* netlists-disp_vhdl: minor rework.Tristan Gingold2020-01-261-2/+2
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* synth: convert subtype on return. Fix #1116Tristan Gingold2020-01-261-1/+1
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* synth: avoid crash on incorrect slice direction. For #1116Tristan Gingold2020-01-262-1/+10
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* synth: handle function call in names. Fix #1114Tristan Gingold2020-01-251-0/+6
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* synth: improve support of 0-width nets and gates. Fix #1113Tristan Gingold2020-01-254-19/+30
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-98/+194
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* synth-static_oper: handle array-element concatenation.Tristan Gingold2020-01-211-0/+20
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-206-17/+26
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* synth-static_oper: handle element/array concat.Tristan Gingold2020-01-201-0/+20
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* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-7/+49
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* synth-oper: handle more signed comparisons. For #1101Tristan Gingold2020-01-191-9/+93
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* synth-stmts: allow slice within a record element. Fix #1100.Tristan Gingold2020-01-191-4/+0
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* netlists-builders: relax assertion. Fix #1099Tristan Gingold2020-01-191-1/+0
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* synth-expr: remove unused with-ed package.Tristan Gingold2020-01-181-1/+0
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* synth: rewrite to work-around old compiler wrong warning.Tristan Gingold2020-01-181-10/+4
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* synth: fix a typo in a comment.Tristan Gingold2020-01-181-1/+1
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* synth: handle deferred constants. Fix #1096Tristan Gingold2020-01-161-1/+1
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* netlists-disp_vhdl: display memory content in user order.Tristan Gingold2020-01-161-5/+6
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* netlists-memories: fix split of memory content. FixTristan Gingold2020-01-161-4/+131
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* ynth-inference: refactoring.Tristan Gingold2020-01-161-23/+21
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* synth-decls: add comments.Tristan Gingold2020-01-161-0/+3
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* synth-insts: clear before applying block configuration. Fix #1095Tristan Gingold2020-01-151-0/+2
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* netlists: use a mark and sweep cleanup.Tristan Gingold2020-01-154-1/+126
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* netlists-memories: allow initialized rams. For #1090Tristan Gingold2020-01-131-1/+2
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* synth: improve support for expanded names. For #1090Tristan Gingold2020-01-131-1/+3
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* synth: remove wbound field of bound_type.Tristan Gingold2020-01-137-36/+14
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* synth-insts: handle slice name as actual to unboundedTristan Gingold2020-01-131-0/+20
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* synth-insts: handle unbounded ports in components.Tristan Gingold2020-01-131-39/+49
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* netlists-disp_vhdl: do not display the chain port for mem_rd_sync. For #1087Tristan Gingold2020-01-131-45/+53
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