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synth
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Author
Age
Files
Lines
*
synth: allow constant condition for if-generate statement.
Tristan Gingold
2020-02-17
1
-0
/
+1
*
synth: add mdff.
Tristan Gingold
2020-02-17
4
-12
/
+88
*
netlists-inference: remove useless code.
Tristan Gingold
2020-02-16
1
-10
/
+0
*
synthesis: rework memory inference.
Tristan Gingold
2020-02-16
3
-32
/
+101
*
synth: handle component with ports in different order.
Tristan Gingold
2020-02-13
3
-45
/
+46
*
synth-static_oper: handle more division operands. Fix #1134
Tristan Gingold
2020-02-12
1
-1
/
+2
*
synth: handle null vector for vec-vec concat. Fix #1133
Tristan Gingold
2020-02-11
2
-6
/
+12
*
synth-oper: handle add for (natural, unsigned). Fix #1132
Tristan Gingold
2020-02-11
1
-0
/
+15
*
netlists-memories: handle split memories. Fix #1127
Tristan Gingold
2020-02-11
1
-8
/
+18
*
synth-static_oper: handle xor.
Tristan Gingold
2020-02-10
1
-0
/
+11
*
synth-expr: implement value and val attributes. Fix #1130
Tristan Gingold
2020-02-10
1
-1
/
+39
*
synth: remove remaining clock edge gates after memories.
Tristan Gingold
2020-02-10
2
-0
/
+26
*
netlists-memories: cleanup.
Tristan Gingold
2020-02-10
1
-319
/
+1
*
synth: rework (again) memory inference.
Tristan Gingold
2020-02-10
8
-80
/
+312
*
synth-inference: minor refactoring.
Tristan Gingold
2020-02-06
1
-24
/
+7
*
synth-decls: set a default value to non-assigned signals. Fix #1107
Tristan Gingold
2020-02-05
1
-1
/
+3
*
netlists-disp_vhdl: handle 1-bit const_x. For #1107
Tristan Gingold
2020-02-05
1
-3
/
+9
*
synth-inference: use the mux output to detect end of walk. Fix #1122
Tristan Gingold
2020-02-01
1
-1
/
+8
*
synth-oper: handle std_match for slv. Close #1121
Tristan Gingold
2020-01-31
1
-1
/
+2
*
netlists-expands: also handle ror.
Tristan Gingold
2020-01-30
1
-7
/
+24
*
synth: handle some rotation and shifts. Fix #1077
Tristan Gingold
2020-01-30
5
-1
/
+154
*
netlists-disp_vhdl: minor rework.
Tristan Gingold
2020-01-26
1
-2
/
+2
*
synth: convert subtype on return. Fix #1116
Tristan Gingold
2020-01-26
1
-1
/
+1
*
synth: avoid crash on incorrect slice direction. For #1116
Tristan Gingold
2020-01-26
2
-1
/
+10
*
synth: handle function call in names. Fix #1114
Tristan Gingold
2020-01-25
1
-0
/
+6
*
synth: improve support of 0-width nets and gates. Fix #1113
Tristan Gingold
2020-01-25
4
-19
/
+30
*
synth: handle matching comparisons. Fix #1109
Tristan Gingold
2020-01-24
1
-98
/
+194
*
synth-static_oper: handle array-element concatenation.
Tristan Gingold
2020-01-21
1
-0
/
+20
*
synth: add id_abs gate. For #1101
Tristan Gingold
2020-01-20
6
-17
/
+26
*
synth-static_oper: handle element/array concat.
Tristan Gingold
2020-01-20
1
-0
/
+20
*
synth: handle more signed operations. For #1101
Tristan Gingold
2020-01-19
1
-7
/
+49
*
synth-oper: handle more signed comparisons. For #1101
Tristan Gingold
2020-01-19
1
-9
/
+93
*
synth-stmts: allow slice within a record element. Fix #1100.
Tristan Gingold
2020-01-19
1
-4
/
+0
*
netlists-builders: relax assertion. Fix #1099
Tristan Gingold
2020-01-19
1
-1
/
+0
*
synth-expr: remove unused with-ed package.
Tristan Gingold
2020-01-18
1
-1
/
+0
*
synth: rewrite to work-around old compiler wrong warning.
Tristan Gingold
2020-01-18
1
-10
/
+4
*
synth: fix a typo in a comment.
Tristan Gingold
2020-01-18
1
-1
/
+1
*
synth: handle deferred constants. Fix #1096
Tristan Gingold
2020-01-16
1
-1
/
+1
*
netlists-disp_vhdl: display memory content in user order.
Tristan Gingold
2020-01-16
1
-5
/
+6
*
netlists-memories: fix split of memory content. Fix
Tristan Gingold
2020-01-16
1
-4
/
+131
*
ynth-inference: refactoring.
Tristan Gingold
2020-01-16
1
-23
/
+21
*
synth-decls: add comments.
Tristan Gingold
2020-01-16
1
-0
/
+3
*
synth-insts: clear before applying block configuration. Fix #1095
Tristan Gingold
2020-01-15
1
-0
/
+2
*
netlists: use a mark and sweep cleanup.
Tristan Gingold
2020-01-15
4
-1
/
+126
*
netlists-memories: allow initialized rams. For #1090
Tristan Gingold
2020-01-13
1
-1
/
+2
*
synth: improve support for expanded names. For #1090
Tristan Gingold
2020-01-13
1
-1
/
+3
*
synth: remove wbound field of bound_type.
Tristan Gingold
2020-01-13
7
-36
/
+14
*
synth-insts: handle slice name as actual to unbounded
Tristan Gingold
2020-01-13
1
-0
/
+20
*
synth-insts: handle unbounded ports in components.
Tristan Gingold
2020-01-13
1
-39
/
+49
*
netlists-disp_vhdl: do not display the chain port for mem_rd_sync. For #1087
Tristan Gingold
2020-01-13
1
-45
/
+53
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