| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | netlists: add d-latch | Tristan Gingold | 2022-07-12 | 3 | -2/+38 |
| * | Fix access check failed from iir_kind_selected_element (#2132) | Michael Nolan | 2022-07-12 | 1 | -0/+1 |
| * | synth-environment: do inference during wire finalization | Tristan Gingold | 2022-07-11 | 1 | -13/+31 |
| * | synth-environment: add Loc parameter to Add_Conc_Assign | Tristan Gingold | 2022-07-11 | 3 | -4/+13 |
| * | netlists-inference: detect false loops only for variables. Fix #2125 | Tristan Gingold | 2022-07-11 | 1 | -2/+3 |
| * | netlists-disp_verilog: do not connect to null-range output. For #2113 | Tristan Gingold | 2022-07-08 | 1 | -41/+47 |
| * | netlists-disp_verilog: fix output for id_abs. For #2123 | Tristan Gingold | 2022-07-06 | 1 | -1/+2 |
| * | synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129 | Tristan Gingold | 2022-07-06 | 1 | -1/+3 |
| * | Fix issue #2126, add handling of to_ux01 to synthesis | Michael Nolan | 2022-07-05 | 1 | -1/+3 |
| * | synth-vhdl_insts: do not crash on unconnected input. Fix #2124 | Tristan Gingold | 2022-07-05 | 1 | -0/+4 |
| * | netlists-disp_verilog: handle Id_Abs. Fix #2113 | Tristan Gingold | 2022-07-04 | 1 | -1/+1 |
| * | synth-vhdl_insts: also handled unbounded records in hash names. | Tristan Gingold | 2022-07-02 | 1 | -0/+7 |
| * | netlists-disp_verilog: adjust, discard null signals. For #2113 | Tristan Gingold | 2022-06-28 | 1 | -1/+6 |
| * | netlists-disp_verilog: fix warning | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | synth/netlists-disp_verilog: skip null input port. Fix #2113 | Tristan Gingold | 2022-06-27 | 1 | -15/+20 |
| * | synth: rework #2109 - remove null wires | Tristan Gingold | 2022-06-27 | 7 | -26/+85 |
| * | synth/netlists-disp_verilog: adjust previous patch. For #2109 | Tristan Gingold | 2022-06-27 | 1 | -1/+2 |
| * | netlists-disp_verilog: do not display ports of width 0. Fix #2109 | Tristan Gingold | 2022-06-27 | 1 | -5/+19 |
| * | synth-vhdl_insts(synth_single_input_assoc): handle type conversion. | Tristan Gingold | 2022-06-16 | 2 | -4/+13 |
| * | Add comments | Tristan Gingold | 2022-06-15 | 1 | -1/+1 |
| * | netlists-rename: handle handle signal instances. Fix #2093 | Tristan Gingold | 2022-06-15 | 3 | -2/+28 |
| * | src/synth: add netlists.rename to rename identifiers. Fix #2054 | Tristan Gingold | 2022-06-14 | 3 | -2/+130 |
| * | netlists-disp_verilog: do not display blackboxes. Fix #2092 | Tristan Gingold | 2022-06-13 | 1 | -0/+5 |
| * | netlists-disp_verilog: Use blocking assignments in non-clocked blocks | Anton Blanchard | 2022-06-13 | 1 | -10/+10 |
| * | synth-vhdl_insts: handle actual conversion function. Fix #2090 | Tristan Gingold | 2022-06-12 | 1 | -12/+38 |
| * | elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089 | Tristan Gingold | 2022-06-12 | 2 | -7/+18 |
| * | elab-vhdl_types(Synth_Array_Attribute): handle dimension parameter | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
| * | synth-environment(Merge_Dyn_Insert): disable transformation. | Tristan Gingold | 2022-06-11 | 1 | -1/+3 |
| * | netlists-memories: handle negation for In_Conjunction. Fix #2086 | Tristan Gingold | 2022-06-11 | 1 | -8/+3 |
| * | synth-vhdl_eval: add support for more operations | Tristan Gingold | 2022-06-11 | 1 | -1/+10 |
| * | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 2 | -6/+23 |
| * | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 7 | -30/+64 |
| * | vhdl-annotations: avoid a crash with subtype attribute in array. | Tristan Gingold | 2022-06-09 | 2 | -3/+9 |
| * | synth-vhdl_expr.adb: use base type for indexed names. Fix #2083 | Tristan Gingold | 2022-06-08 | 1 | -1/+2 |
| * | synth-vhdl_expr: add an hook for signal attributes | Tristan Gingold | 2022-06-08 | 2 | -0/+11 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-07 | 1 | -8/+17 |
| * | elab-vhdl_context: also handle generic subprograms | Tristan Gingold | 2022-06-07 | 1 | -2/+6 |
| * | errorout: add nowrite warning. Fix #2081 | Tristan Gingold | 2022-06-07 | 4 | -8/+11 |
| * | synth-vhdl_stmts: fix handling of instantiated subprograms | Tristan Gingold | 2022-06-06 | 1 | -1/+3 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-06 | 1 | -1/+16 |
| * | synth-vhdl_stmts: handle alias in assignment expression | Tristan Gingold | 2022-06-06 | 3 | -2/+24 |
| * | synth-vhdl_eval: recognize and handle to_stdulogicvector | Tristan Gingold | 2022-06-06 | 1 | -2/+4 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-05 | 2 | -37/+112 |
| * | synth-vhdl_eval: handle more operations (sgn/uns reduce) | Tristan Gingold | 2022-06-05 | 1 | -6/+16 |
| * | synth-vhdl-eval: handle more operations | Tristan Gingold | 2022-06-05 | 4 | -31/+272 |
| * | synth-vhdl_oper: handle more bit_vector operations. Fix #2074 | Tristan Gingold | 2022-06-05 | 1 | -8/+13 |
| * | elab-debugger: add where command | Tristan Gingold | 2022-06-05 | 1 | -28/+49 |
| * | synth-vhdl_eval: handle rotations and shift for numeric_std | Tristan Gingold | 2022-06-05 | 1 | -4/+40 |
| * | synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_x | Tristan Gingold | 2022-06-05 | 2 | -19/+56 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-06-05 | 3 | -2/+41 |
