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* synth: handle constants in assignments. Fix for #1080Tristan Gingold2020-01-123-1/+11
* synth-expr: handle pos attribute. For #1080Tristan Gingold2020-01-121-0/+12
* synth: use formal instance to evaluate default value. For #1080Tristan Gingold2020-01-121-1/+4
* netlists-disp_vhdl: handle one bit memories. Fix #1083Tristan Gingold2020-01-121-2/+6
* netlists: Handle sdiv and udiv (#1082)Anton Blanchard2020-01-111-0/+6
* synth: add --expect-failure for command --synthTristan Gingold2020-01-111-1/+2
* synth-cleanup: avoid a crash on undriven output. Fix #1078Tristan Gingold2020-01-111-3/+5
* synth: fix crash on else-generate. Fix #1076Tristan Gingold2020-01-111-3/+10
* synth: emit error message in case of 'else' for synchronous code. Fix #1074Tristan Gingold2020-01-101-10/+10
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-0/+14
* synth: consider ports size to create unique instances.Tristan Gingold2020-01-103-49/+143
* synth: emit an error in case of static assertion failure. Fix #1068Tristan Gingold2020-01-091-1/+1
* synth-oper: handle xor for bit_vectors.Tristan Gingold2020-01-091-3/+4
* synth: simplify support of inertial associations.Tristan Gingold2020-01-092-4/+14
* synth: improve support of out/inout variable parameters.Tristan Gingold2020-01-083-9/+69
* synth: handle scalar inout association for subprograms. Fix #1064Tristan Gingold2020-01-021-0/+2
* synth-disp_vhdl: handle conversion from signed integers.Tristan Gingold2020-01-011-1/+5
* synth: optimize integer mod for power of 2.Tristan Gingold2020-01-011-0/+24
* synth-inference: merge reset for sub-nets.Tristan Gingold2019-12-311-1/+16
* synth-environment: also optimize mux merge for sub-nets.Tristan Gingold2019-12-313-1/+34
* netlists-disp_vhdl: display iadff.Tristan Gingold2019-12-312-7/+19
* synth: handle wire assigned to a static value. Fix #1058Tristan Gingold2019-12-293-9/+104
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-282-1/+5
* synth: handle is_x (as false). Fix #1054Tristan Gingold2019-12-241-0/+4
* netlists-disp_vhdl: handle conversion from std_logic to signed/unsigned.Tristan Gingold2019-12-242-8/+20
* netlists-memories: add convert_to_memory.Tristan Gingold2019-12-241-298/+504
* synth: add minor comments.Tristan Gingold2019-12-232-1/+3
* synth: add Get_Input_Instance.Tristan Gingold2019-12-144-10/+21
* netlists-memories: add comments.Tristan Gingold2019-12-141-2/+44
* netlists-memories: remove unused subprograms.Tristan Gingold2019-12-081-318/+0
* netlists-memories: reduce muxes.Tristan Gingold2019-12-081-1/+162
* synth: rework in netlists-memories.Tristan Gingold2019-12-061-61/+128
* netlists-disp_vhdl: handle 1-bit add/sub.Tristan Gingold2019-12-051-4/+12
* netlists-memories: avoid a crash when no read. Fix #1018Tristan Gingold2019-12-051-1/+7
* netlists-disp_vhdl: handle more ROMs.Tristan Gingold2019-12-051-2/+12
* netlists-memories: improve ROM inference. For issue #1008Tristan Gingold2019-12-051-26/+48
* netlists-dump: adjust can_inline after cleanup ofTristan Gingold2019-12-051-4/+20
* netlists-memories: generate mem_rd_sync gates.Tristan Gingold2019-12-052-170/+142
* netlists-gates: add comments.Tristan Gingold2019-12-051-3/+13
* netlists-disp_vhdl: handle id_mem_rd_syncTristan Gingold2019-12-051-0/+15
* netlists: add enable port to id_mem_rd_sync.Tristan Gingold2019-12-052-10/+20
* netlists: add remove_output_gates.Tristan Gingold2019-12-053-0/+31
* netlists-memories: rework.Tristan Gingold2019-12-053-3/+857
* synth: add set_location_maybe (for roms).Tristan Gingold2019-12-053-2/+35
* netlists-disp_vhdl: handle unconnected outputs. Fix #1050Tristan Gingold2019-12-041-10/+10
* synth: create unique instance name. Fix #1007Tristan Gingold2019-12-032-4/+155
* synth: add static neg for signed.Tristan Gingold2019-12-033-0/+42
* synth: support multiple synthesis.Tristan Gingold2019-12-023-3/+15
* synth: handle static float unary +, abs and exp. For #1044.Tristan Gingold2019-12-011-0/+7
* synth-insts: use current prefix for instantiations. Fix #1048Tristan Gingold2019-12-011-1/+2
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