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synth
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*
synth: handle generic mapped interface package
Tristan Gingold
2023-01-12
1
-5
/
+17
*
vhdl: clear associated_type in Sem_Generic_Association_Chain
Tristan Gingold
2023-01-12
1
-0
/
+7
*
elab-vhdl_annotations(annotate_interface_list_subtype): adjust
Tristan Gingold
2023-01-12
1
-3
/
+15
*
synth: fix handle of protected type bodies within instantiated packages.
Tristan Gingold
2023-01-12
1
-2
/
+8
*
elab-vhdl_types: improve handling of record subtypes
Tristan Gingold
2023-01-12
2
-18
/
+27
*
synth: handle operator as conversion function
Tristan Gingold
2023-01-12
1
-1
/
+13
*
synth: report values in bound errors
Tristan Gingold
2023-01-12
1
-8
/
+23
*
synth: use same wording for direction mismatch as simulation
Tristan Gingold
2023-01-12
1
-1
/
+2
*
synth-vhdl_eval: handle to_X01 for bit to std_ulogic.
Tristan Gingold
2023-01-11
2
-0
/
+12
*
synth: handle entity attributes
Tristan Gingold
2023-01-11
1
-2
/
+18
*
synth: handle universal r*i and i*r mul, physical mod.
Tristan Gingold
2023-01-11
1
-1
/
+9
*
synth: handle element attribute
Tristan Gingold
2023-01-11
4
-9
/
+39
*
synth: fix matching comparaison tables
Tristan Gingold
2023-01-11
1
-27
/
+27
*
synth: rework error handling in file operations
Tristan Gingold
2023-01-11
3
-43
/
+63
*
synth: improve support of PSL endpoints
Tristan Gingold
2023-01-11
3
-3
/
+6
*
synth: avoid a crash on very large object types
Tristan Gingold
2023-01-11
1
-0
/
+3
*
synth: check float ranges in subtype conversion
Tristan Gingold
2023-01-11
3
-2
/
+25
*
synth: add a check for v87 concatenations
Tristan Gingold
2023-01-11
1
-1
/
+6
*
synth: support constant declarations in protected types
Tristan Gingold
2023-01-11
1
-0
/
+1
*
synth: handle file subtype
Tristan Gingold
2023-01-11
2
-1
/
+9
*
simul: improve support of psl in debugger
Tristan Gingold
2023-01-11
1
-0
/
+3
*
synth: allow file declaration in protected objects
Tristan Gingold
2023-01-11
1
-1
/
+2
*
elab-vhdl_files: remove incorrect assertion
Tristan Gingold
2023-01-11
1
-1
/
+0
*
simul: improve assertion messages for psl
Tristan Gingold
2023-01-11
1
-23
/
+30
*
synth: avoid a crash after error on signal association
Tristan Gingold
2023-01-11
1
-2
/
+6
*
synth: also elaborate dependencies of configurations
Tristan Gingold
2023-01-11
1
-0
/
+4
*
synth: fix memory allocation in predefined function calls
Tristan Gingold
2023-01-10
3
-1
/
+8
*
synth: adjust unshare_type for unbounded composite types
Tristan Gingold
2023-01-10
1
-4
/
+14
*
synth: check rem/mod by 0
Tristan Gingold
2023-01-10
1
-2
/
+14
*
synth: handle indexes in arrays conversion
Tristan Gingold
2023-01-10
4
-15
/
+83
*
synth: add comments, minor rewrite
Tristan Gingold
2023-01-10
2
-2
/
+5
*
synth: also fix #2299
Tristan Gingold
2023-01-10
1
-3
/
+6
*
synth-vhdl_aggr: optimize common aggregate
Tristan Gingold
2023-01-10
1
-11
/
+30
*
Dot output ports (#2305)
cderrien
2023-01-10
1
-53
/
+127
*
synth: always create shared variables
Tristan Gingold
2023-01-09
2
-13
/
+20
*
synth: improve support of individual association for subprograms
Tristan Gingold
2023-01-09
1
-1
/
+2
*
synth-vhdl_aggr: improve support of very large aggregates
Tristan Gingold
2023-01-09
1
-1
/
+2
*
synth: improve support of subtype attribute
Tristan Gingold
2023-01-09
1
-4
/
+4
*
elab-vhdl_expr(exec_name_subtype): handle image attribute
Tristan Gingold
2023-01-09
1
-0
/
+8
*
synth: handle stop/finish without status
Tristan Gingold
2023-01-09
1
-1
/
+3
*
synth: fix handle of array attributes
Tristan Gingold
2023-01-09
1
-7
/
+6
*
synth-vhdl_stmts: handle indexes in image attribute
Tristan Gingold
2023-01-09
1
-5
/
+8
*
synth: handle subtype attribute in type prefixes.
Tristan Gingold
2023-01-09
3
-12
/
+21
*
synth: fix handling of extended enumeration identifiers.
Tristan Gingold
2023-01-09
1
-1
/
+24
*
synth: fix handling of formal slices in individual associations
Tristan Gingold
2023-01-09
1
-2
/
+4
*
synth: allow finalization of protected bodies
Tristan Gingold
2023-01-09
1
-0
/
+2
*
synth: rework value attribute
Tristan Gingold
2023-01-09
3
-108
/
+173
*
synth: handle value attribute for physical types
Tristan Gingold
2023-01-06
1
-0
/
+73
*
synth: use same error message for null access as simulation
Tristan Gingold
2023-01-06
2
-2
/
+2
*
elab-vhdl_debug: makes work and std visible
Tristan Gingold
2023-01-05
1
-4
/
+17
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