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* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
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* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
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* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
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* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
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* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
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* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-093-9/+14
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-052-25/+28
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* synth: Support alias declarations in vunittmeissner2021-11-023-5/+14
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* synth: do full elaboration before synthesisTristan Gingold2021-11-0158-1996/+5291
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* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
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* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
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* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
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* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-2/+4
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* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
| | | | And add comments
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
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* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
| | | | For ghdl/ghdl-yosys-plugin#159
* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
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* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
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* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-151-18/+0
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* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
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* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-121-7/+2
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* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
| | | | Fix #1859
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+2
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* netlists-cleanup: avoid crash when keep attribute value is a stringTristan Gingold2021-09-071-2/+39
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* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
| | | | For #1850
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
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* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
| | | | For #1832
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
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* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
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* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
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* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
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* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
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* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
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* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-281-0/+3
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* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
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* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
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* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | For ghdl/ghdl-yosys-plugin#154
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
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* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-244-19/+0
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-3/+4
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* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-303-10/+11
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* synth-vhdl_context.adb(Is_Full): consider fractional words.Tristan Gingold2021-06-231-2/+16
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* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
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* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-214-25/+59
| | | | Simplifies memory extraction
* synth-vhdl_stmts: merge static extract before dyn_extract.Tristan Gingold2021-06-211-4/+2
| | | | No reasons to use an extra gate.
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