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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-28 10:11:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-28 13:22:29 +0200 |
| commit | f09b7440f071bc5544baa692b3b4c1018a7f905c (patch) | |
| tree | df53c7b04f409645876e25b6ea8a9cce430d24ce /src/synth | |
| parent | 14fd4f9e22e0e0a4320559925ae74ee52b7b35e9 (diff) | |
| download | ghdl-f09b7440f071bc5544baa692b3b4c1018a7f905c.tar.gz ghdl-f09b7440f071bc5544baa692b3b4c1018a7f905c.tar.bz2 ghdl-f09b7440f071bc5544baa692b3b4c1018a7f905c.zip | |
netlists-disp_verilog: handle initial value for idff and isignal
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 28d473a89..55f64d68c 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -802,11 +802,16 @@ package body Netlists.Disp_Verilog is when Id_Signal => Disp_Template (" assign \o0 = \i0; // (signal)" & NL, Inst); when Id_Isignal => - if Get_Driver (Get_Input (Inst, 0)) /= No_Net then - -- It is possible (and meaningful) to have unassigned - -- isignal. - Disp_Template (" assign \o0 = \i0; // (isignal)" & NL, Inst); - end if; + declare + Inet : constant Net := Get_Input_Net (Inst, 0); + begin + if Inet /= No_Net then + Disp_Template (" always @*" & NL & + " \o0 = \i0; // (isignal)" & NL, Inst); + end if; + Disp_Template (" initial" & NL & + " \o0 <= \i1;" & NL, Inst); + end; when Id_Port => Disp_Template (" \o0 <= \i0; -- (port)" & NL, Inst); when Id_Nop => @@ -895,9 +900,13 @@ package body Netlists.Disp_Verilog is " else" & NL & " \o0 <= \i1;" & NL, Inst); when Id_Dff - | Id_Idff => + | Id_Idff => Disp_Template (" always @(\ei0)" & NL & - " \o0 <= \i1;" & NL, Inst); + " \o0 <= \i1;" & NL, Inst); + if Id = Id_Idff then + Disp_Template (" initial" & NL & + " \o0 <= \i2;" & NL, Inst); + end if; when Id_Mux2 => Disp_Template (" assign \o0 = \i0 ? \i2 : \i1;" & NL, Inst); when Id_Mux4 => @@ -1152,7 +1161,8 @@ package body Netlists.Disp_Verilog is when Id_Dff | Id_Idff | Id_Adff - | Id_Iadff => + | Id_Iadff + | Id_Isignal => -- As expected Put (" reg "); when Id_Mux4 |