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* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-0/+6
* synth: move procedure call copyback values in contextTristan Gingold2022-05-253-79/+82
* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-251-12/+2
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-258-72/+203
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-2412-56/+52
* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
* synth-vhdl_eval: handle element-element concatenationTristan Gingold2022-05-241-0/+18
* elab-vhdl_values-debug: slightly improve outputTristan Gingold2022-05-241-2/+6
* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
* synth-vhdl_oper: add an hook for rising_edgeTristan Gingold2022-05-233-4/+13
* elab-vhdl_objtypes: replace Is_Synth by WkindTristan Gingold2022-05-223-23/+40
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-229-70/+36
* synth: also use one-dimensional unbounded arrays for objtypesTristan Gingold2022-05-226-58/+66
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-2214-131/+107
* elab-vhdl_values-debug: improve debug_typ outputTristan Gingold2022-05-221-14/+37
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-2217-552/+340
* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-212-14/+29
* synth-vhdl_expr: avoid a memocy copyTristan Gingold2022-05-211-3/+7
* synth/elab-vhdl_values: use a proper type for signal_indexTristan Gingold2022-05-195-7/+11
* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
* elab-vhdl_context: remove cur_stmt from contextTristan Gingold2022-05-172-21/+0
* synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
* synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062Tristan Gingold2022-05-171-0/+1
* elab-vhdl_debug(disp_instance_path): can also display componentsTristan Gingold2022-05-162-7/+23
* elab-vhdl_debug: factorize code, make Put_Dir publicTristan Gingold2022-05-162-12/+6
* elab-vhdl_values: rename signal_index to signal_index_typeTristan Gingold2022-05-153-5/+5
* elab-vhdl_values-debug: add disp_type_shortTristan Gingold2022-05-152-8/+58
* elab-vhdl_debug: improve info signalsTristan Gingold2022-05-151-20/+19
* elab-debugger: add append_info_menu, to_numTristan Gingold2022-05-152-5/+50
* elab-vhdl_debug(disp_instance_path): show top-level unitTristan Gingold2022-05-151-13/+5
* elab-debugger: add append_menu_commandTristan Gingold2022-05-152-7/+29
* synth: elab-debugger__on.adb is now elab-debugger.adbTristan Gingold2022-05-152-975/+929
* grt: simplifies grt-readline, adjust casingTristan Gingold2022-05-151-6/+4
* elab-vhdl_stmts: change parent of generate_body for for-generateTristan Gingold2022-05-141-1/+1
* ghdlsimul: add and improve debuggerTristan Gingold2022-05-145-25/+461
* elab-vhdl_context: add get_instance_parentTristan Gingold2022-05-142-0/+10
* fix: avoid "pragma Unreferenced given" warnings with GCC 12Xiretza2022-05-141-1/+1
* fix: avoid "unnecessary with of ancestor [-gnatwr]" with GCC 12Xiretza2022-05-142-3/+0
* synth: implement file_open with statusTristan Gingold2022-05-123-0/+69
* synth-vhdl_stmts: export synth_targetTristan Gingold2022-05-122-35/+39
* synth-vhdl_expr: add an hook to get the value of a signalTristan Gingold2022-05-122-0/+9
* elab-vhdl_debug: also disp declarations in instancesTristan Gingold2022-05-121-4/+1
* elab-memtype.adb: identationTristan Gingold2022-05-121-1/+1
* synth: handle text file writeTristan Gingold2022-05-113-0/+93
* synth: add a flag to force creation of variablesTristan Gingold2022-05-115-9/+21
* synth: add current_stmt, minor reworkTristan Gingold2022-05-094-61/+99
* synth-vhdl_insts: handle interfaces of type interface type. Fix #2053Tristan Gingold2022-05-071-1/+12
* elab-vhdl_context: introduce signal_indexTristan Gingold2022-05-063-3/+12
* synth-vhdl_context: resize table before access. Fix #2049Tristan Gingold2022-05-021-6/+14
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