| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: fix handling of record constraints in subtype. Fix #1961 | Tristan Gingold | 2022-02-22 | 1 | -1/+9 |
| * | elab-vhdl_values.adb: fix a typo. Fix #1968 | Tristan Gingold | 2022-02-18 | 1 | -2/+2 |
| * | synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977 | Tristan Gingold | 2022-02-17 | 1 | -27/+30 |
| * | synth: properly propagate bound errors. Fix #1972 | Tristan Gingold | 2022-02-17 | 4 | -16/+38 |
| * | synth-vhdl_oper: handle bit condition operator. Fix #1971 | Tristan Gingold | 2022-02-16 | 1 | -1/+2 |
| * | synth-vhdl_aggr: fix mismatch. Fix #1962 | Tristan Gingold | 2022-02-05 | 1 | -1/+6 |
| * | synth: fix handling of std_logic_unsigned."-" for negative numbers. | Tristan Gingold | 2022-01-18 | 1 | -8/+12 |
| * | synth: adjust handling of subprogram calls in package instantiation. Fix #1947 | Tristan Gingold | 2022-01-16 | 1 | -3/+14 |
| * | synth: do not annotate generic types in package. Fix #1949 | Tristan Gingold | 2022-01-15 | 1 | -11/+19 |
| * | synth: handle macro-expanded package body. Fix #1948 | Tristan Gingold | 2022-01-14 | 2 | -2/+4 |
| * | synth: handle alias of alias. Fix #1945 | Tristan Gingold | 2022-01-12 | 1 | -2/+15 |
| * | synth: refine handling of interface type. Fix #1944 | Tristan Gingold | 2022-01-10 | 1 | -2/+6 |
| * | synth: ignore use clauses in finalization Fix #1942 | Tristan Gingold | 2022-01-05 | 1 | -0/+2 |
| * | synth: handle package instantiation in declarations. Fix #1938 | Tristan Gingold | 2022-01-03 | 4 | -1/+12 |
| * | synth: add assertions | Tristan Gingold | 2021-12-19 | 1 | -0/+4 |
| * | ghdldrv: fix crash due to double initialization | Tristan Gingold | 2021-12-19 | 1 | -2/+0 |
| * | synth: handle interface type in generics. For #412 | Tristan Gingold | 2021-12-15 | 3 | -25/+41 |
| * | Fix opening files relative to the current vhdl | Matt Johnston | 2021-12-07 | 1 | -0/+2 |
| * | synth: add --latches option to enable latches. Fix #938 | Tristan Gingold | 2021-12-06 | 2 | -1/+8 |
| * | synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926 | Tristan Gingold | 2021-11-29 | 1 | -19/+11 |
| * | synth memories: also accept constant signal as memory initial value | Tristan Gingold | 2021-11-28 | 2 | -4/+9 |
| * | elab-vhdl_objtypes.adb: add an assertion | Tristan Gingold | 2021-11-28 | 1 | -0/+2 |
| * | elab-vhdl_insts.adb: do not try to elaborate foreign instances twice | Tristan Gingold | 2021-11-28 | 1 | -1/+6 |
| * | synth-vhdl_insts.adb: split synth_Instantiate_Module | Tristan Gingold | 2021-11-28 | 1 | -14/+26 |
| * | synth: add hooks to support elaboration of foreign instances | Tristan Gingold | 2021-11-28 | 10 | -32/+108 |
| * | synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920 | Tristan Gingold | 2021-11-21 | 1 | -0/+7 |
| * | synth: put direction into port desc | Tristan Gingold | 2021-11-17 | 8 | -31/+30 |
| * | synth: use a global table for instances attributes | Tristan Gingold | 2021-11-17 | 6 | -168/+117 |
| * | synth: renaming to instance_attributes. | Tristan Gingold | 2021-11-17 | 11 | -66/+72 |
| * | synth/netlists-disp_verilog: display port attributes | Tristan Gingold | 2021-11-17 | 1 | -18/+42 |
| * | synth: add ports attributes | Tristan Gingold | 2021-11-17 | 3 | -0/+120 |
| * | Add comments | Tristan Gingold | 2021-11-17 | 1 | -0/+2 |
| * | synth: defer instantations elaboration to handle recursion. Fix #1912 | Tristan Gingold | 2021-11-16 | 2 | -15/+110 |
| * | synth: handle syn_black_box attribute in vhdl architectures | Tristan Gingold | 2021-11-13 | 1 | -10/+75 |
| * | synth: add exec_name_subtype. Fix #1911 | Tristan Gingold | 2021-11-13 | 3 | -4/+52 |
| * | synth: do not display black boxes | Tristan Gingold | 2021-11-12 | 1 | -1/+6 |
| * | synth: also handle rol. For #1909 | Tristan Gingold | 2021-11-11 | 1 | -0/+5 |
| * | synth: handle ror from numeric_std. Fix #1909 | Tristan Gingold | 2021-11-11 | 1 | -1/+4 |
| * | vhdl: Iir_Kind_Foreign_Module is now a library unit | Tristan Gingold | 2021-11-09 | 3 | -9/+14 |
| * | vhdl/psl: handle PSL inherit spec. For #1899 | Tristan Gingold | 2021-11-05 | 2 | -25/+28 |
| * | synth: Support alias declarations in vunit | tmeissner | 2021-11-02 | 3 | -5/+14 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 58 | -1996/+5291 |
| * | synth: reject wait statement. Fix #1903 | Tristan Gingold | 2021-10-29 | 1 | -0/+3 |
| * | synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896 | Tristan Gingold | 2021-10-18 | 1 | -1/+5 |
| * | synth: Support PSL declarations in inline PSL | tmeissner | 2021-10-14 | 1 | -1/+2 |
| * | synth: add support for sequence instance in vunit. Fix #1889 | Tristan Gingold | 2021-10-13 | 1 | -2/+4 |
| * | synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886 | Tristan Gingold | 2021-10-10 | 1 | -42/+74 |
| * | synth-vhdl_expr: fix handling of negative factor in slice. For #1886 | Tristan Gingold | 2021-10-09 | 1 | -25/+61 |
| * | synth-vhdl_decls.adb: also detect unassigned variables. | Tristan Gingold | 2021-10-09 | 1 | -11/+4 |
| * | netlists-disp_verilog: fix name for memory initialization | Tristan Gingold | 2021-09-28 | 1 | -3/+4 |
