| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth_conditiona_signal_assignment: handle simple case directly. | Tristan Gingold | 2023-03-14 | 1 | -46/+79 |
| * | synth: support selected signal assignment | Tristan Gingold | 2023-03-09 | 1 | -0/+2 |
| * | synth-vhdl_oper: handle to_01. Fix #2372 | Tristan Gingold | 2023-03-05 | 1 | -0/+1 |
| * | synth-vhdl_stmts: handle unaffected in conditional variable assignments | Tristan Gingold | 2023-03-02 | 1 | -3/+11 |
| * | synth-vhd_oper: handle rising_edge for bit. For #2369 | Tristan Gingold | 2023-03-02 | 1 | -8/+11 |
| * | synth: handle unaffected in simple sequential signal assignment. | Tristan Gingold | 2023-02-25 | 1 | -4/+9 |
| * | synth-vhdl_expr: improve subtype conversion | Tristan Gingold | 2023-02-22 | 1 | -69/+160 |
| * | synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vector | Tristan Gingold | 2023-02-09 | 3 | -0/+43 |
| * | synth: preliminary work for PSL endpoints | Tristan Gingold | 2023-02-08 | 1 | -0/+17 |
| * | simul: improve support of PSL endpoints | Tristan Gingold | 2023-02-08 | 1 | -2/+11 |
| * | simul: improve handling of individual signal associations | Tristan Gingold | 2023-02-08 | 1 | -3/+3 |
| * | synth: do not handle null-vectors for to_hstring. | Tristan Gingold | 2023-02-08 | 2 | -1/+18 |
| * | synth: use same layout for records in memory as translate | Tristan Gingold | 2023-02-08 | 8 | -68/+227 |
| * | synth: preliminary work to compute access bounds size | Tristan Gingold | 2023-02-05 | 3 | -2/+128 |
| * | elab-vhdl_objtypes: rename acc_bnd_sz to acc_type_sz | Tristan Gingold | 2023-02-05 | 3 | -7/+7 |
| * | elab-vhdl_debug: handle package in subprograms | Tristan Gingold | 2023-02-04 | 1 | -0/+13 |
| * | translate: rework translate_object_subtype_indication. | Tristan Gingold | 2023-02-02 | 1 | -5/+5 |
| * | elab-debugger: also pass top instance on break_time | Tristan Gingold | 2023-01-31 | 2 | -3/+3 |
| * | synth: avoid a crash after errors in declarations. Fix #2334 | Tristan Gingold | 2023-01-30 | 1 | -18/+28 |
| * | synth: also fix crash for #2333 | Tristan Gingold | 2023-01-30 | 1 | -2/+4 |
| * | simul: use same packing order for nets and for values. | Tristan Gingold | 2023-01-30 | 4 | -13/+47 |
| * | elab-debugger: improve current context for print command | Tristan Gingold | 2023-01-30 | 3 | -6/+17 |
| * | elab-vhdl_debug: avoid a crash for lh | Tristan Gingold | 2023-01-30 | 1 | -0/+3 |
| * | netlists-rename: add comments | Tristan Gingold | 2023-01-30 | 1 | -0/+2 |
| * | synth: represent access types as pointers in memory | Tristan Gingold | 2023-01-29 | 13 | -60/+125 |
| * | synth: simplify New_Sname_Artificial (prefix is not used) | Tristan Gingold | 2023-01-29 | 4 | -78/+72 |
| * | elab-vhdl_annotations: refactoring | Tristan Gingold | 2023-01-29 | 1 | -35/+9 |
| * | vhdl: add Is_Owned_Subtype_Indication | Tristan Gingold | 2023-01-29 | 1 | -21/+10 |
| * | synth: avoid a crash on subtype indication. Fix #2330 | Tristan Gingold | 2023-01-29 | 1 | -1/+1 |
| * | synth: handle bit reduction operators. Fix #2328 | Tristan Gingold | 2023-01-29 | 1 | -7/+14 |
| * | synth: improve support of interface type | Tristan Gingold | 2023-01-28 | 2 | -30/+82 |
| * | elab-vhdl_annotations: remove useless code | Tristan Gingold | 2023-01-28 | 1 | -18/+0 |
| * | synth-vhdl_eval: minor reformatting | Tristan Gingold | 2023-01-28 | 1 | -18/+18 |
| * | synth: fix incorrect check in array subtype indications | Tristan Gingold | 2023-01-28 | 1 | -2/+8 |
| * | synth-vhdl_oper: add bit-vect and vect-bit operations. | Tristan Gingold | 2023-01-27 | 1 | -12/+24 |
| * | elab-memtype: add Read_Ptr, Write_Ptr | Tristan Gingold | 2023-01-27 | 2 | -0/+22 |
| * | grt-files_operations: use grt.files | Tristan Gingold | 2023-01-27 | 2 | -4/+5 |
| * | synth: add a check for bounds compatibility | Tristan Gingold | 2023-01-25 | 1 | -4/+39 |
| * | elab-vhdl_debug: add 'info lib' and 'info units' | Tristan Gingold | 2023-01-21 | 1 | -0/+78 |
| * | elab-vhdl_debug: disp generate block declarations | Tristan Gingold | 2023-01-20 | 1 | -2/+4 |
| * | elab-vhdl_debug: disp process declarations | Tristan Gingold | 2023-01-20 | 1 | -0/+10 |
| * | synth: create sub-instace for processes | Tristan Gingold | 2023-01-20 | 4 | -6/+17 |
| * | elab: Rename Get/Set_Info to Get/Set_Ann | Tristan Gingold | 2023-01-20 | 4 | -58/+59 |
| * | synth: add partial support of foreign subprograms | Tristan Gingold | 2023-01-20 | 3 | -2/+341 |
| * | simul: handle PSL endpoints | Tristan Gingold | 2023-01-18 | 2 | -0/+9 |
| * | synth-vhdl_eval: add an overflow check | Tristan Gingold | 2023-01-16 | 1 | -2/+6 |
| * | synth: emit an error message on foreign subprogram calls | Tristan Gingold | 2023-01-16 | 1 | -0/+11 |
| * | synth: handle invididual assoc with unbounded formals | Tristan Gingold | 2023-01-16 | 1 | -6/+130 |
| * | synth: avoid a crash on instantiation | Tristan Gingold | 2023-01-15 | 1 | -4/+19 |
| * | synth: avoid a crash on use before elaboration | Tristan Gingold | 2023-01-15 | 1 | -8/+16 |
