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* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
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* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
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* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-151-18/+0
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* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
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* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-121-7/+2
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* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
| | | | Fix #1859
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+2
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* netlists-cleanup: avoid crash when keep attribute value is a stringTristan Gingold2021-09-071-2/+39
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* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
| | | | For #1850
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
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* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
| | | | For #1832
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
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* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
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* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
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* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
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* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
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* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
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* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-281-0/+3
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* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
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* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
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* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | For ghdl/ghdl-yosys-plugin#154
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
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* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-244-19/+0
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-3/+4
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* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-303-10/+11
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* synth-vhdl_context.adb(Is_Full): consider fractional words.Tristan Gingold2021-06-231-2/+16
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* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
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* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-214-25/+59
| | | | Simplifies memory extraction
* synth-vhdl_stmts: merge static extract before dyn_extract.Tristan Gingold2021-06-211-4/+2
| | | | No reasons to use an extra gate.
* synth-vhdl_expr: adjust width of memidx for indexed names.Tristan Gingold2021-06-211-1/+1
| | | | In general the width of memidx is ignored, but it's better to correctly set it
* synth: add a gate on an optimization to simplify memory handling.Tristan Gingold2021-06-172-67/+38
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* netlists-memories: strengthen dyn_extract mux reduction. Fix #1781Tristan Gingold2021-06-162-1/+52
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* synth: minor fixesTristan Gingold2021-06-152-9/+8
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* netlists-memories: avoid a crash on uninitialized ROM.Tristan Gingold2021-05-241-1/+9
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* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
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* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-072-1/+26
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* netlists-cleanup: do not remove self-assigned output gateTristan Gingold2021-05-071-23/+30
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* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
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* synth: add verilog outputTristan Gingold2021-04-282-0/+1417
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* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-2814-45/+49
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* synth: use a generic version of synth-environment.Tristan Gingold2021-04-2718-363/+479
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* synth-insts.adb: avoid a crash after an error during instantiation. Fix #1734Tristan Gingold2021-04-232-1/+9
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* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
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* synth-vhdl_oper.adb: adjust previous patch and testTristan Gingold2021-04-211-1/+12
| | | | | resize with two signed parameters extract the size of the second parameter to resize the first one.
* synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731Tristan Gingold2021-04-211-0/+1
| | | | With an hint from T.Meissner
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-2115-124/+193
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