| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-vhdl_stmts: export synth_target | Tristan Gingold | 2022-05-12 | 1 | -0/+39 |
| * | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 1 | -0/+2 |
| * | synth: add current_stmt, minor rework | Tristan Gingold | 2022-05-09 | 1 | -0/+14 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -9/+7 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+167 |
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index : iCE40/ghdl | |
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