| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: also handle rol. For #1909 | Tristan Gingold | 2021-11-11 | 1 | -0/+5 |
| * | synth: handle ror from numeric_std. Fix #1909 | Tristan Gingold | 2021-11-11 | 1 | -1/+4 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -1/+4 |
| * | synth-vhdl_oper: handle nor for boolean | Tristan Gingold | 2021-09-14 | 1 | -0/+1 |
| * | synth: add build2_concat2 and use it for vhdl concat. | Tristan Gingold | 2021-08-28 | 1 | -4/+4 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -2/+2 |
| * | synth-vhdl_oper.adb: handle resize uns/uns. For #1731 | Tristan Gingold | 2021-04-21 | 1 | -0/+12 |
| * | synth-vhdl_oper.adb: adjust previous patch and test | Tristan Gingold | 2021-04-21 | 1 | -1/+12 |
| * | synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731 | Tristan Gingold | 2021-04-21 | 1 | -0/+1 |
| * | synth: extract synth-memtype from synth-objtypes | Tristan Gingold | 2021-04-21 | 1 | -0/+1 |
| * | synth: renaming (synth.oper -> synth.vhdl_oper) | Tristan Gingold | 2021-04-16 | 1 | -0/+2151 |
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index : iCE40/ghdl | |
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