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path: root/src/synth/synth-vhdl_insts.adb
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* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-6/+80
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-2/+2
* synth/elab-vhdl_values: add Value_TerminalTristan Gingold2022-07-251-0/+1
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-161-0/+1
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-161-4/+10
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-251-1/+2
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-241-2/+2
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-1/+1
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-5/+14
* synth-vhdl_insts: handle interfaces of type interface type. Fix #2053Tristan Gingold2022-05-071-1/+12
* synth-vhdl_insts: also finalize entity declarationsTristan Gingold2022-04-061-0/+1
* synth: handle individual assoc of unbounded interface. Fix #2023Tristan Gingold2022-04-041-1/+1
* synth: handle concatenation of unbounded types. Fix #1993Tristan Gingold2022-03-081-1/+3
* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-171-2/+3
* synth: add assertionsTristan Gingold2021-12-191-0/+4
* synth: handle interface type in generics. For #412Tristan Gingold2021-12-151-22/+28
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-281-28/+35
* synth: put direction into port descTristan Gingold2021-11-171-3/+3
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-336/+74
* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-151-18/+0
* synth: factorize code to create base instanceTristan Gingold2021-08-281-8/+25
* synthesis.adb: abstract instance_passesTristan Gingold2021-08-281-21/+1
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-8/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-3/+4
* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-301-1/+1
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-281-0/+1752