| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920 | Tristan Gingold | 2021-11-21 | 1 | -0/+7 |
| * | synth: Support alias declarations in vunit | tmeissner | 2021-11-02 | 1 | -1/+3 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -236/+48 |
| * | synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886 | Tristan Gingold | 2021-10-10 | 1 | -42/+74 |
| * | synth-vhdl_expr: fix handling of negative factor in slice. For #1886 | Tristan Gingold | 2021-10-09 | 1 | -25/+61 |
| * | synth: improve result of is_positive | Tristan Gingold | 2021-08-29 | 1 | -3/+5 |
| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -3/+0 |
| * | synth-vhdl_expr: adjust width of memidx for indexed names. | Tristan Gingold | 2021-06-21 | 1 | -1/+1 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+2572 |
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index : iCE40/ghdl | |
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