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path: root/src/synth/synth-vhdl_decls.adb
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* synth: fix handle of protected type bodies within instantiated packages.Tristan Gingold2023-01-121-2/+8
* synth: support constant declarations in protected typesTristan Gingold2023-01-111-0/+1
* synth: allow file declaration in protected objectsTristan Gingold2023-01-111-1/+2
* synth: always create shared variablesTristan Gingold2023-01-091-7/+8
* synth: allow finalization of protected bodiesTristan Gingold2023-01-091-0/+2
* synth-vhdl_decls: manually elaborate protected type bodyTristan Gingold2023-01-041-5/+26
* synth: add support for nested packagesTristan Gingold2023-01-021-7/+70
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-1/+1
* Added id to warnings related to attributes. (#2242)cderrien2022-11-081-1/+3
* simul: complete concurrent procedure callsTristan Gingold2022-10-061-2/+0
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-031-0/+3
* simul: finalize declarations of procedure callsTristan Gingold2022-10-011-0/+2
* synth: handle error on variable default valueTristan Gingold2022-09-271-0/+5
* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-251-1/+3
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-6/+7
* synth: ignore groups and group templatesTristan Gingold2022-09-251-0/+5
* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-171-0/+11
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-171-3/+7
* synth: handle protected types in subprogramsTristan Gingold2022-09-171-7/+45
* synth: finalize filesTristan Gingold2022-09-171-1/+2
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-4/+2
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-18/+47
* simul: add support for protected objectsTristan Gingold2022-09-081-2/+8
* synth: use areapoolsTristan Gingold2022-09-021-2/+6
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-4/+3
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-2/+2
* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-091-5/+8
* errorout: add nowrite warning. Fix #2081Tristan Gingold2022-06-071-3/+5
* synth-vhdl_decls: fix subtype conversion for variable default value.Tristan Gingold2022-06-041-1/+1
* elab-vhdl_objtypes: replace Is_Synth by WkindTristan Gingold2022-05-221-1/+1
* synth-vhdl_decls: handle attributes on input portsTristan Gingold2022-04-291-2/+10
* synth: handle shared variable without default value.Tristan Gingold2022-04-041-0/+3
* synth: handle macro-expanded package body. Fix #1948Tristan Gingold2022-01-141-1/+2
* synth: handle alias of alias. Fix #1945Tristan Gingold2022-01-121-2/+15
* synth: ignore use clauses in finalization Fix #1942Tristan Gingold2022-01-051-0/+2
* synth: handle package instantiation in declarations. Fix #1938Tristan Gingold2022-01-031-0/+5
* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-1/+1
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-591/+178
* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-6/+0
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-281-0/+1227
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