| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: renaming to instance_attributes. | Tristan Gingold | 2021-11-17 | 1 | -1/+1 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -591/+178 |
| * | synth-vhdl_decls.adb: also detect unassigned variables. | Tristan Gingold | 2021-10-09 | 1 | -11/+4 |
| * | synth-vhdl_decls.adb: add comments | Tristan Gingold | 2021-08-28 | 1 | -0/+4 |
| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -6/+0 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+1227 |
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index : iCE40/ghdl | |
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