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path: root/src/synth/synth-insts.adb
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* synth-insts: set location on ports. For #1387Tristan Gingold2020-07-021-0/+2
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-1/+1
* synth: refine -dm debug option. Add -dm2Tristan Gingold2020-05-311-1/+1
* synth: create abstractions for Pval (from synth-insts to synth-decls)Tristan Gingold2020-05-201-39/+2
* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-151-17/+25
* synth: handle vhdl-08 ports. Fix ghdl/ghdl-yosys-plugin#111Tristan Gingold2020-05-071-7/+21
* synth: revert a previous commit: remove the En parameter.Tristan Gingold2020-05-061-25/+16
* synth: remove Global_Context (cleanup).Tristan Gingold2020-05-041-1/+1
* synth: reduce use of global context.Tristan Gingold2020-05-041-7/+11
* synth: propagate enable condition to expressions. For #1273Tristan Gingold2020-05-011-16/+24
* synth: add many calls to set_locationTristan Gingold2020-04-261-3/+9
* synth-insts: factorize code.Tristan Gingold2020-04-231-16/+17
* synth: support -v option.Tristan Gingold2020-04-221-0/+5
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-1/+1
* synth-insts: fix a crash on subtype indication of blackbox components.Tristan Gingold2020-04-191-7/+9
* synth: also try to open files (during synthesis) relative to current unit.Tristan Gingold2020-04-131-0/+5
* synth: refactoring to store static values in wires.Tristan Gingold2020-04-091-6/+8
* synth: extract synth.objtypes from synth.values.Tristan Gingold2020-04-091-0/+1
* synth: handle configuration_specification. Fix #1197Tristan Gingold2020-04-061-4/+4
* synth-debugger: update, handle frame leave.Tristan Gingold2020-04-061-1/+1
* synth: add value_memory and use it to store objects value.Tristan Gingold2020-04-061-39/+28
* synth: more cleanup (and use of valtyp).Tristan Gingold2020-04-021-15/+15
* synth: rework - use valtyp for expressions.Tristan Gingold2020-04-021-52/+51
* synth-insts: keep module/generics/ports case for blackboxes.Tristan Gingold2020-03-311-23/+52
* synth: preliminary work to export module parameters.Tristan Gingold2020-03-311-5/+103
* synth-expr: handle any object for array attributes.Tristan Gingold2020-03-261-49/+0
* synth: improve propagation of errors.Tristan Gingold2020-03-251-7/+17
* synth: preliminary work for package instantiation. For #1159Tristan Gingold2020-03-231-45/+1
* synth: add id_inout gate to handle inout behaviour. Fir #1166Tristan Gingold2020-03-231-13/+31
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-12/+25
* synth-insts: also handle indexed name for synth_type_of_object. Fix #1164Tristan Gingold2020-03-191-0/+8
* synth-insts: handle record in generics.Tristan Gingold2020-03-131-12/+22
* synth-insts: handle output individual assoc for components.Tristan Gingold2020-03-131-18/+3
* synth-insts: handle input individual associations for components.Tristan Gingold2020-03-131-55/+49
* synthesis: handle initialized output ports.Tristan Gingold2020-03-071-3/+17
* synth: top entity name is not anymore hashed by default.Tristan Gingold2020-03-011-73/+88
* synth-insts: add comments, minor refactoring.Tristan Gingold2020-02-291-5/+2
* synth-insts: handle slices in individual associations.Tristan Gingold2020-02-181-0/+21
* synth-expr: handle anonymous signal declarations.Tristan Gingold2020-02-181-4/+4
* synth: handle component with ports in different order.Tristan Gingold2020-02-131-15/+18
* synth: remove remaining clock edge gates after memories.Tristan Gingold2020-02-101-0/+2
* synth-insts: clear before applying block configuration. Fix #1095Tristan Gingold2020-01-151-0/+2
* netlists: use a mark and sweep cleanup.Tristan Gingold2020-01-151-1/+2
* synth-insts: handle slice name as actual to unboundedTristan Gingold2020-01-131-0/+20
* synth-insts: handle unbounded ports in components.Tristan Gingold2020-01-131-39/+49
* synth: use formal instance to evaluate default value. For #1080Tristan Gingold2020-01-121-1/+4
* synth: consider ports size to create unique instances.Tristan Gingold2020-01-101-49/+86
* synth: simplify support of inertial associations.Tristan Gingold2020-01-091-0/+8
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-1/+1
* netlists: add remove_output_gates.Tristan Gingold2019-12-051-0/+1
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