| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: extract synth.objtypes from synth.values. | Tristan Gingold | 2020-04-09 | 1 | -1/+1 |
| * | synth: add value_memory and use it to store objects value. | Tristan Gingold | 2020-04-06 | 1 | -2/+2 |
| * | synth: rework - use valtyp for expressions. | Tristan Gingold | 2020-04-02 | 1 | -2/+2 |
| * | synth-disp_vhdl: do not wrap inout ports. For #1166 | Tristan Gingold | 2020-03-22 | 1 | -3/+12 |
| * | synth: improve support of 0-width nets and gates. Fix #1113 | Tristan Gingold | 2020-01-25 | 1 | -2/+8 |
| * | synth-disp_vhdl: handle conversion from signed integers. | Tristan Gingold | 2020-01-01 | 1 | -1/+5 |
| * | synth: rework the sname API. | Tristan Gingold | 2019-11-28 | 1 | -1/+1 |
| * | introduce package utils_io. | Tristan Gingold | 2019-11-21 | 1 | -0/+1 |
| * | synth-disp_vhdl: handle arrays for in-converters. | Tristan Gingold | 2019-11-12 | 1 | -1/+20 |
| * | synth-disp_vhdl: fix incorrect code for record of width | Tristan Gingold | 2019-10-08 | 1 | -1/+3 |
| * | synth-disp_vhdl: handle array/record of 1 element. | Tristan Gingold | 2019-10-08 | 1 | -3/+11 |
| * | synth-disp_vhdl: handle enum of width 1 for | Tristan Gingold | 2019-10-07 | 1 | -2/+6 |
| * | synth-disp_vhdl: handle in conversions from bitvector. Fix #940 | Tristan Gingold | 2019-09-25 | 1 | -0/+5 |
| * | synth-disp_vhdl: handle disp conversion with bits (and boolean). | Tristan Gingold | 2019-09-25 | 1 | -5/+17 |
| * | synth-disp_vhdl: improve support of boolean, suv. | Tristan Gingold | 2019-09-15 | 1 | -17/+16 |
| * | synth: improve support of negative integer values. | Tristan Gingold | 2019-09-11 | 1 | -1/+6 |
| * | synth: Add width field in type_type record. | Tristan Gingold | 2019-09-11 | 1 | -4/+4 |
| * | synth-disp_vhdl: handle arrays in disp_out_converter. | Tristan Gingold | 2019-09-05 | 1 | -1/+19 |
| * | synth-disp_vhdl: handle records for outputs. | Tristan Gingold | 2019-09-04 | 1 | -42/+76 |
| * | synth-disp_vhdl: handle record for input ports. | Tristan Gingold | 2019-09-03 | 1 | -29/+91 |
| * | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 1 | -1/+2 |
| * | synth: handle integers for displaying vhdl ports. | Tristan Gingold | 2019-08-16 | 1 | -0/+10 |
| * | add synthesis support for logic operators on numeric types (#893) | Pepijn de Vos | 2019-08-15 | 1 | -0/+11 |
| * | synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr. | Tristan Gingold | 2019-08-08 | 1 | -3/+12 |
| * | synth: handle more conversions in disp_vhdl | Tristan Gingold | 2019-07-29 | 1 | -1/+44 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -0/+231 |
