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* synth: simplify New_Sname_Artificial (prefix is not used)Tristan Gingold2023-01-291-1/+1
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-151-1/+4
* synth: put direction into port descTristan Gingold2021-11-171-1/+4
* synth: use a global table for instances attributesTristan Gingold2021-11-171-25/+0
* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-9/+11
* synth: add ports attributesTristan Gingold2021-11-171-0/+15
* netlists: do not remove net gates that have an attributeTristan Gingold2021-03-171-3/+6
* update license headersumarcor2021-02-051-5/+3
* std_names: add gclk. For #1610Tristan Gingold2021-01-251-0/+2
* netlists: complete support of attributes. For #1318Tristan Gingold2020-05-231-3/+19
* netlists: use dyn_maps package for attributes.Tristan Gingold2020-05-221-12/+8
* netlists: add param_pval_boolean.Tristan Gingold2020-05-221-3/+3
* netlists: initial support of attributes.Tristan Gingold2020-05-211-6/+27
* netlists: initial infrastructure for attributes. For #1318Tristan Gingold2020-05-191-3/+19
* netlists: make free_instance private and remove_instance public.Tristan Gingold2020-05-181-6/+4
* netlists: add disp_stats.Tristan Gingold2020-05-181-0/+3
* netlists: add more flags in Module_Record.Tristan Gingold2020-05-181-15/+23
* Makefile: Generate Param_Pval_* in ghdlsynth_gates.hTristan Gingold2020-03-311-1/+8
* synth: preliminary work to export module parameters.Tristan Gingold2020-03-311-2/+35
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-1/+4
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-0/+2
* netlists: use C convention to pass records.Tristan Gingold2019-11-281-0/+4
* netlists: remove port API (make it easier to interface).Tristan Gingold2019-11-281-8/+8
* netlists: remove port_inout.Tristan Gingold2019-11-281-4/+1
* synth: rework the sname API.Tristan Gingold2019-11-281-4/+3
* synth/netlists: remove unused function.Tristan Gingold2019-11-281-1/+0
* netlists-dump: display ports name.Tristan Gingold2019-11-111-0/+3
* netlists: add 2 flags per instance, including a mark flag.Tristan Gingold2019-11-111-6/+15
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-271-0/+3
* netlists: add remove_instance.Tristan Gingold2019-10-161-0/+3
* synth: rewrite cleanup pass.Tristan Gingold2019-10-101-0/+13
* netlists: remove get_parent for instance.Tristan Gingold2019-10-061-2/+0
* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-061-1/+0
* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-061-1/+0
* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-061-1/+0
* netlists: Remove Get_Name renaming for instances.Tristan Gingold2019-10-061-1/+0
* synth-inference: detect false loop.Tristan Gingold2019-09-171-0/+4
* synth: use original entity to display netlist.Tristan Gingold2019-07-231-0/+3
* synth: remove bounds (unused) for ports.Tristan Gingold2019-07-221-4/+0
* synth: add concatn gateTristan Gingold2019-07-191-0/+8
* netlists: add a comment.Tristan Gingold2019-06-301-0/+11
* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-281-2/+0
* synth: add get_input_net helper.Tristan Gingold2019-06-281-0/+2
* Small typo in netlist.adsPepijn de Vos2019-05-051-1/+1
* [PATCH] synth: add comments.Tristan Gingold2019-04-181-2/+9
* synth: add comments.Tristan Gingold2019-04-161-18/+34
* synth: defer gates removal after at end of entity synthesis.Tristan Gingold2017-02-151-3/+5
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+337
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