iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: minor refactoring about const gates.	Tristan Gingold	2019-09-15	1	-0/+9
*	synth: handle unsigned shift left.	Tristan Gingold	2019-09-11	1	-53/+57
*	synth: add const_x gate.	Tristan Gingold	2019-09-11	1	-0/+1
*	synth: add const_sb32, add smul/umul.	Tristan Gingold	2019-09-07	1	-2/+4
*	synth: remove insert gate.	Tristan Gingold	2019-08-31	1	-7/+0
*	synth: remove unused const gates.	Tristan Gingold	2019-08-30	1	-7/+2
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-1/+5
*	synth: add concatn gate	Tristan Gingold	2019-07-19	1	-0/+3
*	synth: add const_z gate.	Tristan Gingold	2019-07-19	1	-0/+2
*	synth: add Id_Port gate to improve display.	Tristan Gingold	2019-07-10	1	-23/+24
*	netlists: add reduce_or/reduce_and gates.	Tristan Gingold	2019-07-04	1	-0/+2
*	netlists: add assume gate.	Tristan Gingold	2019-07-04	1	-0/+1
*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	1	-0/+3
*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	1	-4/+10
*	synth: add ule, fix gate number.	Tristan Gingold	2019-06-30	1	-29/+29
*	synth: disp_vhdl: handle mux2	Tristan Gingold	2019-06-28	1	-0/+4
*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	1	-1/+7
*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	1	-1/+2
*	synth: add insert gate.	Tristan Gingold	2019-06-24	1	-0/+10
*	synth: use only one edge gate, make it fully abstract. Handle falling_edge.	Tristan Gingold	2019-05-22	1	-5/+4
*	synth: add comments.	Tristan Gingold	2019-04-16	1	-3/+13
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+114