aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth/netlists-builders.adb
Commit message (Expand)AuthorAgeFilesLines
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-0/+1
* netlists-builders: relax assertion. Fix #1099Tristan Gingold2020-01-191-1/+0
* netlists-builders: allow more gates with null bus. For #1080Tristan Gingold2020-01-121-2/+0
* netlists: add enable port to id_mem_rd_sync.Tristan Gingold2019-12-051-7/+14
* netlists: remove port API (make it easier to interface).Tristan Gingold2019-11-281-54/+52
* synth: rework the sname API.Tristan Gingold2019-11-281-55/+86
* netlists: add Get_Design.Tristan Gingold2019-11-281-0/+6
* netlists: initial support of net of width 0.Tristan Gingold2019-11-121-2/+0
* netlists: add dyn_insert_en gate.Tristan Gingold2019-11-111-14/+48
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-051-133/+0
* netlists-builders: add build2_uresize.Tristan Gingold2019-11-031-0/+24
* netlists: add formal input gates.Tristan Gingold2019-10-301-0/+32
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-271-0/+36
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-211-17/+26
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-171-15/+12
* netlists: declare memory gates.Tristan Gingold2019-10-151-3/+159
* netlists-builders: adjust names of dyn_extract ports.Tristan Gingold2019-10-131-2/+2
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-6/+6
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-25/+24
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-9/+4
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-8/+4
* synth: introduce memidx1Tristan Gingold2019-10-021-8/+6
* netlists: add memidx1 and memidx2 gates.Tristan Gingold2019-10-021-0/+77
* synth: add support for integer rem.Tristan Gingold2019-10-011-0/+3
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-011-4/+4
* synth: improve support of * and /. Fix #953Tristan Gingold2019-09-301-0/+6
* synth: add support for mod operator.Tristan Gingold2019-09-281-2/+7
* synth: rework type for expression.Tristan Gingold2019-09-251-1/+3
* synth: handle rotate.Tristan Gingold2019-09-221-10/+14
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-3/+20
* synth: remove value_mux2.Tristan Gingold2019-09-181-3/+5
* synth: add build2_const_vecTristan Gingold2019-09-151-0/+18
* synth: allow empty string literal.Tristan Gingold2019-09-121-1/+0
* synth: handle unsigned shift left.Tristan Gingold2019-09-111-0/+26
* synth: add const_x gate.Tristan Gingold2019-09-111-0/+18
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-2/+53
* synth: remove insert gate.Tristan Gingold2019-08-311-38/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-311-1/+22
* synth: add support for record types.Tristan Gingold2019-08-291-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-201-4/+17
* synth: set location on assume/assert gates.Tristan Gingold2019-08-201-2/+4
* synth: handle signed integer comparisons (#878)Pepijn de Vos2019-08-011-0/+10
* synth: add support for memories.Tristan Gingold2019-07-291-1/+43
* synth: remove bounds (unused) for ports.Tristan Gingold2019-07-221-4/+2
* synth: rework names.Tristan Gingold2019-07-221-2/+3
* synth: add concatn gateTristan Gingold2019-07-191-0/+24
* synth: add const_z gate.Tristan Gingold2019-07-191-2/+21
* synth: add > and >= operators (#870)Pepijn de Vos2019-07-161-0/+5
* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-101-3/+21
* netlists: export new_internal_name.Tristan Gingold2019-07-041-4/+10
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 03:10:07 +0000