index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
synth
/
netlists-builders.adb
Commit message (
Expand
)
Author
Age
Files
Lines
*
synth: simplify New_Sname_Artificial (prefix is not used)
Tristan Gingold
2023-01-29
1
-72
/
+67
*
netlists-builders: allow building mem_wr_sync without clk and en.
Tristan Gingold
2022-11-05
1
-4
/
+10
*
netlists: add d-latch
Tristan Gingold
2022-07-12
1
-0
/
+30
*
synth: put direction into port desc
Tristan Gingold
2021-11-17
1
-5
/
+9
*
synth: handle PSL async_abort and sync_abort. For #1654
Tristan Gingold
2021-08-31
1
-6
/
+8
*
synth: reuse signal name while creating memories. Fix #1838
Tristan Gingold
2021-08-25
1
-5
/
+6
*
update license headers
umarcor
2021-02-05
1
-5
/
+3
*
netlists: preliminary support of memory of depth one.
Tristan Gingold
2020-08-06
1
-2
/
+0
*
synth: handle reduction operators. Fix #1342
Tristan Gingold
2020-05-27
1
-0
/
+2
*
synth: handle initialized inout port. For #1312
Tristan Gingold
2020-05-15
1
-2
/
+19
*
netlists-builders: add Build_Pmux.
Tristan Gingold
2020-05-09
1
-0
/
+29
*
synth: add Id_Enable gate (for sequential assertions).
Tristan Gingold
2020-05-06
1
-0
/
+17
*
netlists: add resolver gate.
Tristan Gingold
2020-04-22
1
-0
/
+18
*
synth: add tri gate.
Tristan Gingold
2020-04-22
1
-0
/
+33
*
synth: rework edge handling to properly support falling edge. Fix #1227
Tristan Gingold
2020-04-15
1
-10
/
+25
*
synth: preliminary support of multiport rams (using shared variable).
Tristan Gingold
2020-03-28
1
-0
/
+24
*
netlists-builders: allow more null nets. Fix #1169
Tristan Gingold
2020-03-23
1
-2
/
+1
*
synth: add id_inout gate to handle inout behaviour. Fir #1166
Tristan Gingold
2020-03-23
1
-0
/
+21
*
synth-disp_vhdl: do not wrap inout ports. For #1166
Tristan Gingold
2020-03-22
1
-0
/
+2
*
netlists: add id_nop gate.
Tristan Gingold
2020-03-22
1
-6
/
+21
*
synth: handle numeric_std minimum/maximum. Fix #1168
Tristan Gingold
2020-03-21
1
-0
/
+9
*
netlists-builders: allow null net for all dffs. Fix #1162
Tristan Gingold
2020-03-19
1
-2
/
+0
*
netlists: handle more case of 0 sized nets.
Tristan Gingold
2020-03-13
1
-2
/
+0
*
netlists: allow empty net for build_mux4
Tristan Gingold
2020-03-09
1
-1
/
+0
*
netlists-builders: handle null operands for dyadic operations.
Tristan Gingold
2020-03-07
1
-1
/
+0
*
synthesis: handle initialized output ports.
Tristan Gingold
2020-03-07
1
-2
/
+21
*
netlists: rework memories to fix port orders, add a loop.
Tristan Gingold
2020-02-23
1
-18
/
+20
*
netlists: add midff
Tristan Gingold
2020-02-20
1
-0
/
+33
*
synth: add mdff.
Tristan Gingold
2020-02-17
1
-1
/
+29
*
synth: avoid crash on incorrect slice direction. For #1116
Tristan Gingold
2020-01-26
1
-1
/
+0
*
synth: improve support of 0-width nets and gates. Fix #1113
Tristan Gingold
2020-01-25
1
-2
/
+0
*
synth: add id_abs gate. For #1101
Tristan Gingold
2020-01-20
1
-0
/
+1
*
netlists-builders: relax assertion. Fix #1099
Tristan Gingold
2020-01-19
1
-1
/
+0
*
netlists-builders: allow more gates with null bus. For #1080
Tristan Gingold
2020-01-12
1
-2
/
+0
*
netlists: add enable port to id_mem_rd_sync.
Tristan Gingold
2019-12-05
1
-7
/
+14
*
netlists: remove port API (make it easier to interface).
Tristan Gingold
2019-11-28
1
-54
/
+52
*
synth: rework the sname API.
Tristan Gingold
2019-11-28
1
-55
/
+86
*
netlists: add Get_Design.
Tristan Gingold
2019-11-28
1
-0
/
+6
*
netlists: initial support of net of width 0.
Tristan Gingold
2019-11-12
1
-2
/
+0
*
netlists: add dyn_insert_en gate.
Tristan Gingold
2019-11-11
1
-14
/
+48
*
synth: extract netlists-folds from netlists-builders.
Tristan Gingold
2019-11-05
1
-133
/
+0
*
netlists-builders: add build2_uresize.
Tristan Gingold
2019-11-03
1
-0
/
+24
*
netlists: add formal input gates.
Tristan Gingold
2019-10-30
1
-0
/
+32
*
synth: create build2_concat from netlists-concat.
Tristan Gingold
2019-10-27
1
-0
/
+36
*
synth: generate cover for assertion precedent.
Tristan Gingold
2019-10-21
1
-17
/
+26
*
synth: add netlists-memories to extract memories. Still WIP.
Tristan Gingold
2019-10-17
1
-15
/
+12
*
netlists: declare memory gates.
Tristan Gingold
2019-10-15
1
-3
/
+159
*
netlists-builders: adjust names of dyn_extract ports.
Tristan Gingold
2019-10-13
1
-2
/
+2
*
netlists: rename id_memidx1 to id_memidx
Tristan Gingold
2019-10-03
1
-6
/
+6
*
synth: replace memidx2 by addidx; handle some 2d arrays.
Tristan Gingold
2019-10-03
1
-25
/
+24
[next]