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synth
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elab-vhdl_stmts.adb
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Author
Age
Files
Lines
*
synth: create sub-instace for processes
Tristan Gingold
2023-01-20
1
-1
/
+1
*
synth: improve support of PSL endpoints
Tristan Gingold
2023-01-11
1
-1
/
+2
*
synth: elaborate case generate statements
Tristan Gingold
2023-01-01
1
-0
/
+35
*
synth: add statement in context, adjust path/instance name attributes
Tristan Gingold
2022-12-31
1
-2
/
+2
*
simul: gather disconnection specifications, create guard signal
Tristan Gingold
2022-09-25
1
-3
/
+3
*
elab-vhdl_stmts: fix a TODO
Tristan Gingold
2022-09-07
1
-1
/
+3
*
synth: handle generics in blocks
Tristan Gingold
2022-09-06
1
-7
/
+22
*
synth: use areapools
Tristan Gingold
2022-09-02
1
-12
/
+28
*
synth: handle indexes/ranges in configurations for generate blocks
Tristan Gingold
2022-08-25
1
-4
/
+28
*
elab-vhdl_expr: factorize code
Tristan Gingold
2022-08-19
1
-2
/
+3
*
vhdl: preliminary work to elaborat quantities
Tristan Gingold
2022-07-16
1
-0
/
+2
*
elab-vhdl_stmts: change parent of generate_body for for-generate
Tristan Gingold
2022-05-14
1
-1
/
+1
*
synth: do full elaboration before synthesis
Tristan Gingold
2021-11-01
1
-0
/
+231