iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	simul: factorize code to compute number of sources	Tristan Gingold	2022-08-23	4	-120/+50
*	simul-vhdl_debug: disp nbr sources	Tristan Gingold	2022-08-23	1	-1/+15
*	simul: add extra drivers for ports without sources	Tristan Gingold	2022-08-23	3	-14/+152
*	simul-vhdl_simul: handle waveforms in signal assignments	Tristan Gingold	2022-08-21	1	-40/+47
*	simul: rework assertions execution and error handling	Tristan Gingold	2022-08-21	1	-3/+4
*	simul: handle concurrent procedure calls (WIP)	Tristan Gingold	2022-08-21	1	-15/+95
*	simul: handle after clauses in signal assignment	Tristan Gingold	2022-08-21	1	-70/+93
*	simul-vhdl_simul: add support for PSL directives	Tristan Gingold	2022-08-20	2	-14/+267
*	simul-vhdl_debug: display connections	Tristan Gingold	2022-08-19	1	-5/+63
*	simul: handle resolved signals (WIP)	Tristan Gingold	2022-08-19	2	-43/+297
*	ghdlsimul: add an option to debug before elaboration	Tristan Gingold	2022-08-18	2	-3/+4
*	simul: handle individual associations	Tristan Gingold	2022-08-17	2	-4/+16
*	simul: add create_connects	Tristan Gingold	2022-08-17	4	-46/+144
*	simul: create terminals (WIP)	Tristan Gingold	2022-08-17	4	-8/+62
*	simul-vhdl_simul: add scalar terminal table	Tristan Gingold	2022-07-28	1	-0/+16
*	simul-vhdl_debug: add info terminal	Tristan Gingold	2022-07-28	1	-20/+69
*	simul: gather terminals	Tristan Gingold	2022-07-25	2	-0/+43
*	src/simul: rewrite of ghdl/simul based on synth	Tristan Gingold	2022-07-24	7	-0/+3759