| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul: handle resolved signals (WIP) | Tristan Gingold | 2022-08-19 | 2 | -43/+297 |
| * | ghdlsimul: add an option to debug before elaboration | Tristan Gingold | 2022-08-18 | 2 | -3/+4 |
| * | simul: handle individual associations | Tristan Gingold | 2022-08-17 | 2 | -4/+16 |
| * | simul: add create_connects | Tristan Gingold | 2022-08-17 | 4 | -46/+144 |
| * | simul: create terminals (WIP) | Tristan Gingold | 2022-08-17 | 4 | -8/+62 |
| * | simul-vhdl_simul: add scalar terminal table | Tristan Gingold | 2022-07-28 | 1 | -0/+16 |
| * | simul-vhdl_debug: add info terminal | Tristan Gingold | 2022-07-28 | 1 | -20/+69 |
| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 2 | -0/+43 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 7 | -0/+3759 |
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index : iCE40/ghdl | |
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