| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+29 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+677 |
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index : iCE40/ghdl | |
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