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* grt-vcd.adb: add option --vcd-4states to dump a strict vcd file. Fix #1759Tristan Gingold2021-09-301-7/+17
* grt-vcd: exclude arrays from dump. Fix #1881Tristan Gingold2021-09-291-59/+67
* vpi: handle get_value for indexed names. Fix #237Tristan Gingold2021-06-101-1/+13
* grt-vcd: add get_vcd_value_kindTristan Gingold2021-06-081-30/+38
* grt-vpi: improve support of arraysTristan Gingold2021-06-071-15/+17
* grt: preliminary work to support arrays in vpiTristan Gingold2021-06-061-17/+30
* update license headersumarcor2021-01-141-11/+9
* grt: fix warnings from gnatgpl2020.Tristan Gingold2020-05-231-1/+3
* Constants in vpi (#1297)Ben Reynwar2020-05-101-1/+2
* grt: extract grt.to_strings from grt.imagesTristan Gingold2019-06-011-3/+3
* Pass time-resolution to grt.Tristan Gingold2018-10-211-1/+15
* Rework translation of unbounded and complex types.Tristan Gingold2018-10-211-1/+2
* grt: rework error API (WIP).Tristan Gingold2018-09-161-1/+1
* vcd: add global scope.Tristan Gingold2018-07-251-33/+32
* grt.fcvt: use format_image instead of to_string (cleanup).Tristan Gingold2017-04-191-1/+1
* Add more testcases for bug069Tristan Gingold2017-04-021-75/+17
* rtis/vcd/ghw: handle record subtypes.Tristan Gingold2017-02-221-16/+22
* unbounded records: add rti support (WIP)Tristan Gingold2017-02-211-2/+2
* Support added for * and **. Please note that wildcards inside names like /top...Jonas Baggett2016-11-021-17/+17
* There is a new --write-opt-file option that will create a wave option file wi...Jonas Baggett2016-11-011-29/+30
* vcd,fst: avoid spurious error message for packages.Tristan Gingold2016-09-031-0/+4
* Extend wave option to VCD and FST #128Jonsba2016-08-031-25/+73
* vpi: handle parameters/generics.Tristan Gingold2016-07-031-113/+115
* grt-vcd: rename vcd_var_kind to vcd_var_type.Tristan Gingold2016-07-031-14/+14
* fst: dump enumerations.Tristan Gingold2016-06-171-66/+93
* Pass signal values to interfaces. 'sigptr' optimization.Tristan Gingold2015-12-181-6/+6
* Rework callbacks, support cocotb.Tristan Gingold2015-10-301-3/+32
* grt: add --list-features, and --has-featureTristan Gingold2015-09-141-1/+2
* vcd/fst: handle complex signals. Fix crash.Tristan Gingold2014-12-211-0/+4
* grt-vcd: in verilog_wire_info, replace addr by sigs.Tristan Gingold2014-12-011-32/+30
* Initial support of FST dump format.Tristan Gingold2014-11-291-2/+1
* Move files and dirs from translate/Tristan Gingold2014-11-051-0/+845
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 10:46:01 +0000
driver` refers to the source of the net using `PortRef`; `driver.cell == nullptr` means that the net is undriven. Nets must have zero or one driver only. The corresponding cell port must be an output and its `PortInfo::net` must refer back to this net. - `users` contains a list of `PortRef` references to sink ports on the net. Nets can have zero or more sinks. Each corresponding cell port must be an input or inout; and its `PortInfo::net` must refer back to this net. - `wires` is a map that stores the routing tree of a net, if the net is routed. - Each entry in `wires` maps from *sink* wire in the routing tree to its driving pip, and the binding strength of that pip (e.g. how freely the router may rip up the pip) - Manipulation of this structure is done automatically by `Arch::bindWire`, `Arch::unbindWire`, `Arch::bindPip` and `Arch::unbindPip`; which should almost always be used in lieu of manual manipulation - `attrs` stores metadata about the wire (which may come from the JSON or be added by passes) - `clkconstr` contains the period constraint if the wire is a constrained clock; or is empty otherwise - `region` is a reference to a `Region` if the net is constrained to a device region or `nullptr` otherwise (_N.B. not supported by the current router_). ## BaseCtx/Context Relevant fields from a netlist point of view are: - `cells` is a map from cell name to a `unique_ptr<CellInfo>` containing cell data - `nets` is a map from net name to a `unique_ptr<NetInfo>` containing net data - `net_aliases` maps every alias for a net to its canonical name (i.e. index into `nets`) - net aliases often occur when a net has a name both inside a submodule and higher level module - `ports` is a list of top level ports, primarily used during JSON export (e.g. to produce a useful post-PnR simulation model). Unlike other ports, top level ports are _not_ added to the driver or users of any connected net. In this sense, nets connected to top-level ports are _dangling_. However, top level ports _can_ still see their connected net as part of their `PortInfo`. Context also has a method `check()` that ensures all of the contracts met above are satisfied. It is strongly suggested to run this after any pass that may modify the netlist. ## Performance Improvements Two features are provided to enable performance improvements in some algorithms, generally by reducing the number of `unordered_map` accesses. The first is `udata`. This is a field of both nets and cells that can be used to give an index into algorithm-specific structures, such as a flat `vector` of cells. Placers and routers may use this for any purpose, but it should not be used to exchange data between passes. The second is `ArchCellInfo` and `ArchNetInfo`. These are provided by architectures and used as base classes for `CellInfo` and `NetInfo` respectively. They allow architectures to tag information that is needed frequently - for example the clock polarity and clock net for a flipflop are needed for placement validity checking. They should only be used inside arch-specific code, and are lost when netlists are saved/loaded thus must not be used as primary storage - usually these should mirror attributes/parameters. `assignArchInfo` should set these up accordingly. ## Helper Functions - Context `Context` and its subclass `BaseCtx` provides several helper functions that are often needed inside CAD algorithms. - `nameOfBel`, `nameOfWire`, and `nameOfPip` gets the name of an identified object as a C string, often used in conjunction with the logging functions - `nameOf` is similar to above but for netlist objects that have a `name` field (e.g. cells, nets, etc) - `getNetinfoSourceWire` gets the physical wire `WireId` associated with the source of a net - `getNetinfoSinkWire` gets the physical wire `WireId` associated with a given sink (specified by `PortRef`) - `getNetinfoRouteDelay` gets the routing delay - actual if the net is fully routed, estimated otherwise - between the source and a given sink of a net - `getNetByAlias` returns the pointer to a net given any of its aliases - this should be used in preference to a direct lookup in `nets` whenever a net name is provided by the user ## Hierarchy As most place and route algorithms require a flattened netlist to work with (consider - each leaf cell instance must have its own bel), the primary netlist structures are flattened. However, some tasks such as floorplanning require an understanding of hierarchy. `HierarchicalCell` is the main data structure for storing hierarchy. This represents an instance of a hierarchical, rather than leaf cell (leaf cells are represented by a `CellInfo`). - `name` and `type` are the instance name and cell type - `parent` is the hierarchical path of the parent cell, and `fullpath` is the hierarchical path of this cell - `leaf_cells`, `nets` map from a name inside the hierarchical cell to a 'global' name in the flattened netlist (i.e. one that indexes into `ctx->{cells,nets}`) - `leaf_cells_by_gname`, `nets_by_gname` are the inverse of the above maps; going from `{CellInfo,NetInfo}::name` to an instance name inside the cell - `hier_cells` maps instance names of sub-hierarchical (non-leaf) cells to global names (indexing into `ctx->hierarchy`) To preserve hierarchy during passes such as packing, ensure that `hierpath` is set on new cells derived from existing ones, and call `fixupHierarchy()` at the end to rebuild `HierarchicalCell` structures.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 10:46:00 +0000