iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-18/+19
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-0/+4
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-4/+14
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-22/+27
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-0/+4
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-131/+132
*	vhdl: recognize div operators.	Tristan Gingold	2019-09-30	1	-90/+96
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	1	-46/+50
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	2	-95/+115
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	1	-46/+50
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	1	-82/+88
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	2	-5/+5
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	1	-91/+95
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	1	-25/+30
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	2	-109/+118
*	synth: handle verification units.	Tristan Gingold	2019-08-20	2	-245/+253
*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-242/+243
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	2	-452/+483
*	vhdl: recognize PSL units reserved words.	Tristan Gingold	2019-08-16	2	-71/+88
*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	2	-276/+268
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	2	-110/+117
*	python: regenerate files.	Tristan Gingold	2019-07-26	1	-66/+76
*	libghdl: import Free_Dependence_List.	Tristan Gingold	2019-07-11	1	-0/+2
*	Fix a merge collision.	Tristan Gingold	2019-07-08	1	-154/+84
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-3/+3
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	2	-21/+96
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-167/+222
*	python: add __init__.py files.	Tristan Gingold	2019-06-25	1	-0/+0
*	Rework libghdl build/install procedure (#840)	1138-4EB	2019-06-17	16	-0/+4636