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* rework 'python', rename to 'pyGHDL'umarcor2020-12-271-1294/+0
* py: run blackeine2020-12-161-707/+397
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-718/+1031
* py: run blackeine2020-09-261-705/+396
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-643/+957
* python: execute 'black'eine2020-08-231-705/+394
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-189/+200
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-3/+3
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-277/+281
* Synthesis of PSL prev function.Tristan Gingold2020-06-021-3/+3
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+12
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-9/+9
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-97/+104
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-141/+145
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-70/+78
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-206/+210
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-287/+375
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-13/+17
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-95/+103
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+3
* synth: handle verification units.Tristan Gingold2019-08-201-245/+249
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-245/+257
* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-272/+268
* Rework libghdl build/install procedure (#840)1138-4EB2019-06-171-0/+1435