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path: root/python/libghdl/thin/vhdl/nodes.py
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* py: run blackeine2020-12-161-16/+49
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* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-470/+453
| | | | | | | | | | | | | Attributes of entity/architecture/configurations are expected to be locally static so that they can be referenced from outside (so on the non-instantiated entity). But many designs break this assumption. In relaxed mode, non-locally static attributes are allowed but now cannot be referenced outside the entity. Locally static attributes can be referenced from outside. Fix #1528
* py: run blackeine2020-09-261-18/+49
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* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-467/+450
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* py: run blackeine2020-09-151-2/+1
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* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-141-232/+269
| | | | Handle them in synthesis.
* python: execute 'black'eine2020-08-231-102/+175
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* vhdl: recognize more operators for std_logic_unsigned/signed.Tristan Gingold2020-08-071-174/+200
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* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-071-116/+128
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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-84/+96
| | | | For #1416
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-2/+2
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-130/+131
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* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-370/+388
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-0/+4
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* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-0/+5
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* Synthesis of PSL prev function.Tristan Gingold2020-06-021-2/+2
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-117/+139
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* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-362/+366
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* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-191-37/+37
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* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-161-81/+81
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-5/+0
| | | | Global renaming.
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-60/+84
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* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-111-151/+152
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* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-92/+94
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* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-12/+60
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* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-0/+4
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* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-0/+12
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* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-221-90/+92
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* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-164/+176
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* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-77/+79
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* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-0/+32
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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-0/+4
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* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-162/+174
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+4
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* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-216/+222
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
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* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-140/+144
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* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-77/+85
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* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-50/+51
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+28
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-28/+45
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-86/+90
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-180/+181
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-29/+39
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* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-454/+625
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+4
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* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-159/+161
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* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-47/+49
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