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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-28 18:31:29 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-28 18:31:29 +0100 |
| commit | e5ce655bd182daaddb5f685f077cb69a416d34c4 (patch) | |
| tree | eb8aba257717258c29b5ea98a8d35fe31a983681 /python/libghdl/thin/vhdl/nodes.py | |
| parent | 5837c03fe6704eff8ba531aafecfd7323ff353c8 (diff) | |
| download | ghdl-e5ce655bd182daaddb5f685f077cb69a416d34c4.tar.gz ghdl-e5ce655bd182daaddb5f685f077cb69a416d34c4.tar.bz2 ghdl-e5ce655bd182daaddb5f685f077cb69a416d34c4.zip | |
vhdl: recognize reduce functions in std_logic_misc.
Diffstat (limited to 'python/libghdl/thin/vhdl/nodes.py')
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 7a9b650c1..9a2a05f60 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1457,6 +1457,18 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 474 Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 475 Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 476 + Ieee_Std_Logic_Misc_And_Reduce_Slv = 477 + Ieee_Std_Logic_Misc_And_Reduce_Suv = 478 + Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 479 + Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 480 + Ieee_Std_Logic_Misc_Or_Reduce_Slv = 481 + Ieee_Std_Logic_Misc_Or_Reduce_Suv = 482 + Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 483 + Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 484 + Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 485 + Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 486 + Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 487 + Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 488 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location |