aboutsummaryrefslogtreecommitdiffstats
path: root/pyGHDL/libghdl/vhdl/nodes.py
Commit message (Expand)AuthorAgeFilesLines
* vhdl: recognize conv_signed. For #2408Tristan Gingold2023-04-141-138/+142
* vhdl: add Owned_Instance_Package_Body to handle ownershipTristan Gingold2023-03-261-0/+13
* vhdl: add Set/Get_Immediate_Body_Flag (for package instantiation)Tristan Gingold2023-03-221-0/+13
* vhdl: add iir_kind_package_instantiation_bodyTristan Gingold2023-03-221-229/+230
* ghdllocal.adb(Build_Dependence): rebuild file dependencies.Tristan Gingold2023-03-131-13/+0
* vhdl: add Get/Set_Elaboration_FlagTristan Gingold2023-01-141-0/+13
* vhdl-sem_inst: handle suspend_stateTristan Gingold2023-01-041-0/+26
* Change needs to be done in pynodes.Patrick Lehmann2022-12-241-0/+9
* Improved doc-strings.Patrick Lehmann2022-12-241-0/+3
* vhdl: add Get/Set_Associated_package. For #2264Tristan Gingold2022-12-181-0/+13
* vhdl-nodes: add Get/Set_Instantiated_Header.Tristan Gingold2022-12-161-0/+13
* vhdl-nodes: add Get/Set_Associated_Subprogram.Tristan Gingold2022-11-301-0/+13
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-212/+213
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-257/+260
* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-101-0/+13
* vhdl: add an owner to interface type definitionTristan Gingold2022-08-071-0/+13
* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-071-0/+26
* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-291-0/+13
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-251-0/+13
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-9/+9
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-4/+12
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-121-0/+13
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-2/+2
* vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-061-218/+240
* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-222/+224
* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-051-458/+481
* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-051-293/+317
* vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-051-226/+234
* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-011-424/+426
* vhdl: recognize numeric_bit.to_unsignedTristan Gingold2022-05-311-220/+226
* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-301-147/+147
* vhdl: recognize subprograms from std.envTristan Gingold2022-05-291-484/+489
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-2/+52
* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-178/+180
* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-11/+19
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-0/+13
* Changed export decorator from pydecor to pyTooling.DecoratorsPatrick Lehmann2021-12-121-1/+1
* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-111-280/+284
* pyGHDL: regenerate nodes.pyTristan Gingold2021-11-101-309/+311
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-5/+0
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-323/+324
* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-0/+13
* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-0/+17
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+13
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-180/+179
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-297/+305
* Fix Codacy problems.Patrick Lehmann2021-07-011-0/+372
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-1/+0
* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-563/+565
* fix more codacy issuesumarcor2021-06-231-2/+1