iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	synth: rework static predefined function calls.	Tristan Gingold	2020-02-18	3	-152/+224
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*	synth: handle file_open.	Tristan Gingold	2020-02-18	3	-0/+48
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*	testsuite/synth: adjust testcase #1078	Tristan Gingold	2020-02-18	1	-1/+1
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*	synth-environment: handle unassigned outputs.	Tristan Gingold	2020-02-18	1	-6/+8
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*	netlists-cleanup: refactoring.	Tristan Gingold	2020-02-18	1	-12/+17
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*	testsuite/synth: add a test for previous commit.	Tristan Gingold	2020-02-18	3	-1/+49
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*	synth-insts: handle slices in individual associations.	Tristan Gingold	2020-02-18	1	-0/+21
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*	testsuite/synth: merge ram01 to mem01, add NOTES.txt	Tristan Gingold	2020-02-18	9	-17/+25
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*	testsuite/synth: add test for #1139	Tristan Gingold	2020-02-18	4	-0/+149
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*	vhdl-sem_scopes: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	1	-1/+2
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*	vhdl-configuration: ignore configuration for top_level_entity.	Tristan Gingold	2020-02-18	1	-4/+4
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*	synth-expr: handle anonymous signal declarations.	Tristan Gingold	2020-02-18	2	-6/+10
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*	testsuite/gna: add tests for previous commit.	Tristan Gingold	2020-02-17	6	-0/+168
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*	vhdl-sem_assocs: recurse for individual associations.	Tristan Gingold	2020-02-17	1	-23/+64
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*	testsuite/synth: add a test for #1076	Tristan Gingold	2020-02-17	4	-1/+156
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*	synth: allow constant condition for if-generate statement.	Tristan Gingold	2020-02-17	1	-0/+1
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*	synth: add mdff.	Tristan Gingold	2020-02-17	4	-12/+88
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*	testsuite/synth: add test for previous commit.	Tristan Gingold	2020-02-16	3	-1/+65
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*	netlists-inference: remove useless code.	Tristan Gingold	2020-02-16	1	-10/+0
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*	synthesis: rework memory inference.	Tristan Gingold	2020-02-16	3	-32/+101
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*	testsuite/gna: add test from #1137	Tristan Gingold	2020-02-15	3	-0/+261
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*	synth: handle component with ports in different order.	Tristan Gingold	2020-02-13	3	-45/+46
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*	vhdl-parse: improve recovery for incorrect end identifier.	Tristan Gingold	2020-02-13	1	-8/+27
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*	files_maps-editor: fix incorrect assertion.	Tristan Gingold	2020-02-13	1	-1/+1
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*	testsuite/gna: add a test for previous commit.	Tristan Gingold	2020-02-13	2	-0/+12
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*	vhdl-sem_expr: avoid a crash on incorrect qualified expr.	Tristan Gingold	2020-02-13	1	-0/+6
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*	synth-static_oper: handle more division operands. Fix #1134	Tristan Gingold	2020-02-12	1	-1/+2
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*	testsuite/synth: add test for #1133	Tristan Gingold	2020-02-11	2	-0/+36
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*	synth: handle null vector for vec-vec concat. Fix #1133	Tristan Gingold	2020-02-11	2	-6/+12
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*	testsuite/synth: add test for #1132	Tristan Gingold	2020-02-11	2	-0/+34
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*	synth-oper: handle add for (natural, unsigned). Fix #1132	Tristan Gingold	2020-02-11	1	-0/+15
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*	testsuite/synth: add more test for #1127	Tristan Gingold	2020-02-11	2	-1/+43
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*	netlists-memories: handle split memories. Fix #1127	Tristan Gingold	2020-02-11	1	-8/+18
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*	testsuite/gna: add a test for #1125	Tristan Gingold	2020-02-11	2	-0/+42
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*	translate: refine condition. Fix #1125	Tristan Gingold	2020-02-11	1	-1/+1
\| \| \| \|	For the check of matching direction in slices.
*	testsuite/synth: add test for #1130.	Tristan Gingold	2020-02-10	2	-0/+33
\| \| \| \|	Fix #1130
*	testsuite/synth: add testcase for #1126	Tristan Gingold	2020-02-10	2	-0/+608
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*	synth-static_oper: handle xor.	Tristan Gingold	2020-02-10	1	-0/+11
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*	testsuite/synth: add testcase for #1130	Tristan Gingold	2020-02-10	2	-0/+41
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*	synth-expr: implement value and val attributes. Fix #1130	Tristan Gingold	2020-02-10	1	-1/+39
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*	grt: split grt-errors, disp current process.	Tristan Gingold	2020-02-10	18	-104/+183
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*	synth: remove remaining clock edge gates after memories.	Tristan Gingold	2020-02-10	2	-0/+26
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*	netlists-memories: cleanup.	Tristan Gingold	2020-02-10	1	-319/+1
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*	synth: rework (again) memory inference.	Tristan Gingold	2020-02-10	8	-80/+312
\| \| \| \| \| \|	Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
*	synth-inference: minor refactoring.	Tristan Gingold	2020-02-06	1	-24/+7
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*	testsuite/synth: add a test for #1107	Tristan Gingold	2020-02-05	2	-0/+26
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*	synth-decls: set a default value to non-assigned signals. Fix #1107	Tristan Gingold	2020-02-05	1	-1/+3
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*	netlists-disp_vhdl: handle 1-bit const_x. For #1107	Tristan Gingold	2020-02-05	1	-3/+9
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*	vhdl-sem_names: improve error location.	Tristan Gingold	2020-02-04	1	-1/+1
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*	vhdl-sem: improve error location for unknown entity.	Tristan Gingold	2020-02-04	1	-1/+1
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