iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	testsuite/gna: add a test for Wuseless warning. For #1832	Tristan Gingold	2021-08-29	2	-0/+26
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*	vhdl-canon: detect PSL assertion that cannot fail. For #1832	Tristan Gingold	2021-08-29	2	-3/+17
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*	testsuite/synth: add a test for #1832	Tristan Gingold	2021-08-29	2	-0/+29
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*	synth-vhdl_stmts: fix a crash on never triggered PSL assertion.	Tristan Gingold	2021-08-29	1	-0/+6
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*	synth: improve result of is_positive	Tristan Gingold	2021-08-29	4	-10/+15
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*	netlists-inference: improve location for dff.	Tristan Gingold	2021-08-29	1	-1/+1
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*	synth: factorize code to create base instance	Tristan Gingold	2021-08-28	7	-57/+104
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*	synthesis.adb: abstract instance_passes	Tristan Gingold	2021-08-28	3	-23/+34
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*	synth-environment: add subprograms for signals (preliminary work)	Tristan Gingold	2021-08-28	2	-5/+110
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*	synth-memtype: export conversion functions	Tristan Gingold	2021-08-28	2	-7/+9
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*	synth: add build2_concat2 and use it for vhdl concat.	Tristan Gingold	2021-08-28	3	-4/+18
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*	ghdlsynth: add debug option for elaboration	Tristan Gingold	2021-08-28	2	-1/+8
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*	synth-vhdl_decls.adb: add comments	Tristan Gingold	2021-08-28	1	-0/+4
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*	vhdl: handle foreign units in libraries and configuration	Tristan Gingold	2021-08-28	3	-24/+45
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*	errorout: do not display empty lines	Tristan Gingold	2021-08-28	3	-1/+14
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*	netlists-disp_verilog: handle initial value for idff and isignal	Tristan Gingold	2021-08-28	1	-8/+18
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*	pyGHDL.dom: improvements (#1848)	Unai Martinez-Corral	2021-08-27	5	-19/+64
\|\ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	# New Features * Translate null statements. * Sequential procedure call. * Concurrent assert statement (but without condition) This needs either PSL translations or help from @tgingold to have partial elaboration to a PSL assert becomes a normal VHDL assertion like in VHDL-93. * Translate sensitivity lists. # Changes * None # Bug fixes * Changes due to typo in pyVHDLModel for `Choises`.
\| *	Updated requirements to pyVHDLModel v0.12.0.	Patrick Lehmann	2021-08-27	1	-2/+2
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\| *	Handle sensitivity lists.	Patrick Lehmann	2021-08-27	1	-4/+3
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\| *	Added concurrent (PSL) assertion.	Patrick Lehmann	2021-08-26	3	-5/+35
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\| *	Translate sequential procedure calls.	Patrick Lehmann	2021-08-26	3	-7/+8
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\| *	Implemented handling off null statements.	Patrick Lehmann	2021-08-26	4	-6/+21
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* \|	testsuite/synth: add a test for #1850	Tristan Gingold	2021-08-27	3	-0/+82
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* \|	vhdl-parse: support for-generate in vunits. Fix #1850	Tristan Gingold	2021-08-27	1	-2/+10
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* \|	testsuite/synth: Add a test for ghdl/ghdl-yosys-plugin#154	Tristan Gingold	2021-08-27	2	-0/+58
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* \|	synth: do not remove signals with a keep attribute.	Tristan Gingold	2021-08-27	2	-1/+31
\| \| \| \| \| \| \| \|	For ghdl/ghdl-yosys-plugin#154
* \|	std_names: add name keep.	Tristan Gingold	2021-08-27	3	-183/+186
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* \|	netlists-disp_verilog: fix handling of unconnected port	Tristan Gingold	2021-08-26	1	-3/+1
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* \|	ghdlsynth.adb: fix a typo	Tristan Gingold	2021-08-26	1	-1/+1
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*	testsuite/gna: add a test for #1832	Tristan Gingold	2021-08-26	2	-0/+132
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*	PSL: handle inf in star repeat sequence. Fix #1832	Tristan Gingold	2021-08-26	9	-11/+44
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*	testsuite/gna: add a reproducer for #1834	Tristan Gingold	2021-08-26	3	-0/+59
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*	vhdl-evaluation: check integer evaluations fit in base type. Fix #1834	Tristan Gingold	2021-08-26	2	-11/+37
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*	testsuite/synth: add a test for #1838	Tristan Gingold	2021-08-25	2	-0/+48
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*	synth: reuse signal name while creating memories. Fix #1838	Tristan Gingold	2021-08-25	5	-20/+34
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*	ortho/gcc: adjust and propagate to all gcc versions the change for #1845	Tristan Gingold	2021-08-25	6	-1/+81
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*	testsuite/gna: add a testcase for #1844	Tristan Gingold	2021-08-25	2	-0/+56
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*	vhdl-sem_types.adb: refine conditions for resolution functions.	Tristan Gingold	2021-08-25	1	-3/+7
\| \| \| \| \| \| \|	Do not consider that functions with unbounded elements can be a resolution function. For #1844
*	ghdldrv: handle auxbase option in ortho/gcc. Fix #1845	Tristan Gingold	2021-08-24	2	-10/+16
\| \| \| \| \|	Remove additional option in ghdldrv.adb, automatically set aux_base_name in ortho-lang-9.c
*	testsuite/gna: add a test for #1814	Tristan Gingold	2021-08-24	3	-0/+72
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*	testsuite/gna: add a test for #1837	Tristan Gingold	2021-08-24	2	-0/+19
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*	vhdl-parse.adb: improve error recovery. For #1837	Tristan Gingold	2021-08-24	1	-0/+2
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*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	23	-643/+377
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*	vhdl-sem_specs: avoid ownership issue on default map aspect.	Tristan Gingold	2021-08-24	1	-1/+4
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*	Changed Debian 'Buster' to 'Bullseye'	Patrick Lehmann	2021-08-23	3	-3/+3
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\| *	Debian Bullseye was released	umarcor	2021-08-23	3	-3/+3
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* \|	Set black formatting to 120 chars per line.	Patrick Lehmann	2021-08-23	33	-757/+234
\|\ \ \| \|/ \|/\|	Added pyproject.toml
\| *	pyGHDL/lsp: style	umarcor	2021-08-23	1	-6/+3
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\| *	black: rerun, to pick pyproject settings	umarcor	2021-08-23	32	-754/+232
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\| *	add pyproject.toml	umarcor	2021-08-23	1	-0/+2
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