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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-28 10:11:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-28 13:22:29 +0200 |
| commit | b8b61eb99f0fdd3a04a3c5be53c0892f17c921e9 (patch) | |
| tree | b8db5e986ca13eb9b22c56e16267c23741c5d5ec | |
| parent | f09b7440f071bc5544baa692b3b4c1018a7f905c (diff) | |
| download | ghdl-b8b61eb99f0fdd3a04a3c5be53c0892f17c921e9.tar.gz ghdl-b8b61eb99f0fdd3a04a3c5be53c0892f17c921e9.tar.bz2 ghdl-b8b61eb99f0fdd3a04a3c5be53c0892f17c921e9.zip | |
errorout: do not display empty lines
| -rw-r--r-- | src/errorout-console.adb | 1 | ||||
| -rw-r--r-- | src/errorout.adb | 10 | ||||
| -rw-r--r-- | src/errorout.ads | 4 |
3 files changed, 14 insertions, 1 deletions
diff --git a/src/errorout-console.adb b/src/errorout-console.adb index 6ae90e272..6a112352c 100644 --- a/src/errorout-console.adb +++ b/src/errorout-console.adb @@ -240,6 +240,7 @@ package body Errorout.Console is and then Flag_Caret_Diagnostics and then (Current_Error.File /= No_Source_File_Entry and Current_Error.Line /= 0) + and then Get_File_Length (Current_Error.File) > 0 then Put_Line (Extract_Expanded_Line (Current_Error.File, Current_Error.Line)); diff --git a/src/errorout.adb b/src/errorout.adb index f0316197e..4f0746fcb 100644 --- a/src/errorout.adb +++ b/src/errorout.adb @@ -419,4 +419,14 @@ package body Errorout is begin return (Kind => Earg_Synth_Name, Val_Lang => V); end Make_Earg_Synth_Name; + + function Make_Earg_Verilog_Node (V : Uns32) return Earg_Type is + begin + return (Kind => Earg_Verilog_Node, Val_Lang => V); + end Make_Earg_Verilog_Node; + + function Make_Earg_Verilog_Token (V : Uns32) return Earg_Type is + begin + return (Kind => Earg_Verilog_Token, Val_Lang => V); + end Make_Earg_Verilog_Token; end Errorout; diff --git a/src/errorout.ads b/src/errorout.ads index d060003ee..0bdd8fb5d 100644 --- a/src/errorout.ads +++ b/src/errorout.ads @@ -254,6 +254,7 @@ package Errorout is Earg_Location, Earg_Id, Earg_Char, Earg_String8, Earg_Uns32, Earg_Int32, Earg_Vhdl_Node, Earg_Vhdl_Token, + Earg_Verilog_Node, Earg_Verilog_Token, Earg_Synth_Instance, Earg_Synth_Net, Earg_Synth_Name); subtype Earg_Lang_Kind is Earg_Kind range Earg_Vhdl_Node .. Earg_Kind'Last; @@ -271,11 +272,12 @@ package Errorout is function Make_Earg_Vhdl_Node (V : Uns32) return Earg_Type; function Make_Earg_Vhdl_Token (V : Uns32) return Earg_Type; + function Make_Earg_Verilog_Node (V : Uns32) return Earg_Type; + function Make_Earg_Verilog_Token (V : Uns32) return Earg_Type; function Make_Earg_Synth_Instance (V : Uns32) return Earg_Type; function Make_Earg_Synth_Net (V : Uns32) return Earg_Type; function Make_Earg_Synth_Name (V : Uns32) return Earg_Type; private - type Earg_Type (Kind : Earg_Kind := Earg_None) is record case Kind is when Earg_None => |