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* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-237-46/+85
* netlists-memories: also reduce muxes for extract.Tristan Gingold2020-02-211-7/+35
* testsuite/synth: add a test for #1144Tristan Gingold2020-02-212-0/+25
* synth-decls: handle alias declaration without subtype indication.Tristan Gingold2020-02-211-2/+7
* testsuite/synth: add a source for mem01Tristan Gingold2020-02-202-0/+31
* netlists-memories: factorize code.Tristan Gingold2020-02-201-235/+191
* netlists-inference: preliminary work to support else in synch code.Tristan Gingold2020-02-201-71/+153
* netlists: add midffTristan Gingold2020-02-203-0/+47
* add build script for termux (#1143)umarcor2020-02-201-0/+15
* disable backtrace on android (#1142)umarcor2020-02-191-1/+1
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-187-417/+485
* synth: rework static predefined function calls.Tristan Gingold2020-02-183-152/+224
* synth: handle file_open.Tristan Gingold2020-02-183-0/+48
* testsuite/synth: adjust testcase #1078Tristan Gingold2020-02-181-1/+1
* synth-environment: handle unassigned outputs.Tristan Gingold2020-02-181-6/+8
* netlists-cleanup: refactoring.Tristan Gingold2020-02-181-12/+17
* testsuite/synth: add a test for previous commit.Tristan Gingold2020-02-183-1/+49
* synth-insts: handle slices in individual associations.Tristan Gingold2020-02-181-0/+21
* testsuite/synth: merge ram01 to mem01, add NOTES.txtTristan Gingold2020-02-189-17/+25
* testsuite/synth: add test for #1139Tristan Gingold2020-02-184-0/+149
* vhdl-sem_scopes: handle anonymous signal declarations.Tristan Gingold2020-02-181-1/+2
* vhdl-configuration: ignore configuration for top_level_entity.Tristan Gingold2020-02-181-4/+4
* synth-expr: handle anonymous signal declarations.Tristan Gingold2020-02-182-6/+10
* testsuite/gna: add tests for previous commit.Tristan Gingold2020-02-176-0/+168
* vhdl-sem_assocs: recurse for individual associations.Tristan Gingold2020-02-171-23/+64
* testsuite/synth: add a test for #1076Tristan Gingold2020-02-174-1/+156
* synth: allow constant condition for if-generate statement.Tristan Gingold2020-02-171-0/+1
* synth: add mdff.Tristan Gingold2020-02-174-12/+88
* testsuite/synth: add test for previous commit.Tristan Gingold2020-02-163-1/+65
* netlists-inference: remove useless code.Tristan Gingold2020-02-161-10/+0
* synthesis: rework memory inference.Tristan Gingold2020-02-163-32/+101
* testsuite/gna: add test from #1137Tristan Gingold2020-02-153-0/+261
* synth: handle component with ports in different order.Tristan Gingold2020-02-133-45/+46
* vhdl-parse: improve recovery for incorrect end identifier.Tristan Gingold2020-02-131-8/+27
* files_maps-editor: fix incorrect assertion.Tristan Gingold2020-02-131-1/+1
* testsuite/gna: add a test for previous commit.Tristan Gingold2020-02-132-0/+12
* vhdl-sem_expr: avoid a crash on incorrect qualified expr.Tristan Gingold2020-02-131-0/+6
* synth-static_oper: handle more division operands. Fix #1134Tristan Gingold2020-02-121-1/+2
* testsuite/synth: add test for #1133Tristan Gingold2020-02-112-0/+36
* synth: handle null vector for vec-vec concat. Fix #1133Tristan Gingold2020-02-112-6/+12
* testsuite/synth: add test for #1132Tristan Gingold2020-02-112-0/+34
* synth-oper: handle add for (natural, unsigned). Fix #1132Tristan Gingold2020-02-111-0/+15
* testsuite/synth: add more test for #1127Tristan Gingold2020-02-112-1/+43
* netlists-memories: handle split memories. Fix #1127Tristan Gingold2020-02-111-8/+18
* testsuite/gna: add a test for #1125Tristan Gingold2020-02-112-0/+42
* translate: refine condition. Fix #1125Tristan Gingold2020-02-111-1/+1
* testsuite/synth: add test for #1130.Tristan Gingold2020-02-102-0/+33
* testsuite/synth: add testcase for #1126Tristan Gingold2020-02-102-0/+608
* synth-static_oper: handle xor.Tristan Gingold2020-02-101-0/+11
* testsuite/synth: add testcase for #1130Tristan Gingold2020-02-102-0/+41