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* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
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* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
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* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
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* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-282-1/+8
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* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
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* vhdl: handle foreign units in libraries and configurationTristan Gingold2021-08-283-24/+45
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* errorout: do not display empty linesTristan Gingold2021-08-283-1/+14
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* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
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* pyGHDL.dom: improvements (#1848)Unai Martinez-Corral2021-08-275-19/+64
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # New Features * Translate null statements. * Sequential procedure call. * Concurrent assert statement (but without condition) This needs either PSL translations or help from @tgingold to have partial elaboration to a PSL assert becomes a normal VHDL assertion like in VHDL-93. * Translate sensitivity lists. # Changes * None # Bug fixes * Changes due to typo in pyVHDLModel for `Choises`.
| * Updated requirements to pyVHDLModel v0.12.0.Patrick Lehmann2021-08-271-2/+2
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| * Handle sensitivity lists.Patrick Lehmann2021-08-271-4/+3
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| * Added concurrent (PSL) assertion.Patrick Lehmann2021-08-263-5/+35
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| * Translate sequential procedure calls.Patrick Lehmann2021-08-263-7/+8
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| * Implemented handling off null statements.Patrick Lehmann2021-08-264-6/+21
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* | testsuite/synth: add a test for #1850Tristan Gingold2021-08-273-0/+82
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* | vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
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* | testsuite/synth: Add a test for ghdl/ghdl-yosys-plugin#154Tristan Gingold2021-08-272-0/+58
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* | synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | | | | | For ghdl/ghdl-yosys-plugin#154
* | std_names: add name keep.Tristan Gingold2021-08-273-183/+186
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* | netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
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* | ghdlsynth.adb: fix a typoTristan Gingold2021-08-261-1/+1
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* testsuite/gna: add a test for #1832Tristan Gingold2021-08-262-0/+132
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* PSL: handle inf in star repeat sequence. Fix #1832Tristan Gingold2021-08-269-11/+44
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* testsuite/gna: add a reproducer for #1834Tristan Gingold2021-08-263-0/+59
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* vhdl-evaluation: check integer evaluations fit in base type. Fix #1834Tristan Gingold2021-08-262-11/+37
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* testsuite/synth: add a test for #1838Tristan Gingold2021-08-252-0/+48
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* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
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* ortho/gcc: adjust and propagate to all gcc versions the change for #1845Tristan Gingold2021-08-256-1/+81
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* testsuite/gna: add a testcase for #1844Tristan Gingold2021-08-252-0/+56
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* vhdl-sem_types.adb: refine conditions for resolution functions.Tristan Gingold2021-08-251-3/+7
| | | | | | | Do not consider that functions with unbounded elements can be a resolution function. For #1844
* ghdldrv: handle auxbase option in ortho/gcc. Fix #1845Tristan Gingold2021-08-242-10/+16
| | | | | Remove additional option in ghdldrv.adb, automatically set aux_base_name in ortho-lang-9.c
* testsuite/gna: add a test for #1814Tristan Gingold2021-08-243-0/+72
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* testsuite/gna: add a test for #1837Tristan Gingold2021-08-242-0/+19
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* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-2423-643/+377
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* vhdl-sem_specs: avoid ownership issue on default map aspect.Tristan Gingold2021-08-241-1/+4
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* Changed Debian 'Buster' to 'Bullseye'Patrick Lehmann2021-08-233-3/+3
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| * Debian Bullseye was releasedumarcor2021-08-233-3/+3
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* | Set black formatting to 120 chars per line.Patrick Lehmann2021-08-2333-757/+234
|\ \ | |/ |/| Added pyproject.toml
| * pyGHDL/lsp: styleumarcor2021-08-231-6/+3
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| * black: rerun, to pick pyproject settingsumarcor2021-08-2332-754/+232
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| * add pyproject.tomlumarcor2021-08-231-0/+2
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* pyGHDL: update to pyVHDLModel v0.11.5 (#1822)Unai Martinez-Corral2021-08-2329-913/+3376
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Features: * Handle multiple identifiers in generics, ports, parameters and objects. * `ghdl-dom` now also accepts `-D` for directories to scan. * Resolve architectures to entities. * Context reference * Library clause * Use clause * Handle contexts of design units * New `OpenName` * Translate concurrent statements: * Component instantiation * Entity instantiation * Configuration instantiation * If..generate statement * Case..generate statement * For..generate statement * Block statement * Process statement * Concurrent simple signal assignment * Concurrent procedure call * Translate sequential statements: * If statement * Case statement * For loop * Sequential simple signal assignment * Sequential procedure call * Sequential assert statement * Sequential report statement * Wait statement * Print hierarchy in pretty-print * New binding to `str_table` `string8_address` Changes: * Adjusted to renaming of `pyVHDLModel.VHDLModel` to `pyVHDLModel.SyntaxModel`. * Adjust DOM to a change in pyVHDLModel: some Identifiers being now a list of identifiers. * Reordered items in GHA workflow `Test.yml`. * Improved ranges Bug fixes: * Fixed typo in IIR translation of `Greater_Than_Or_Equal_Operator`: should be `GreaterEqualExpression`. * Wrap type marks in a `SimpleName`. * Fixed syntax of lists in GHA workflow `Test.yml`. * Fixed handling of bit-string literals.
| * Skip null statement.Patrick Lehmann2021-08-232-1/+8
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| * Fixes due to a bug in pyVHDLModel. Name Context was used twice.Patrick Lehmann2021-08-2311-100/+108
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| * Some fixes.Patrick Lehmann2021-08-235-21/+21
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| * ci: styleumarcor2021-08-231-8/+21
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| * Fixed case statement.Patrick Lehmann2021-08-232-7/+3
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| * Handle subprogram vs. subprogram body.Patrick Lehmann2021-08-231-7/+45
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