aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-0110-62/+110
* testsuite/synth: add testcase for #956Tristan Gingold2019-09-302-0/+32
* synth: handle range defined by high/low attributes. Fix #956Tristan Gingold2019-09-301-2/+2
* testsuite/synth: add testcase for #953Tristan Gingold2019-09-302-0/+24
* synth: improve support of * and /. Fix #953Tristan Gingold2019-09-303-2/+46
* vhdl: recognize div operators.Tristan Gingold2019-09-303-90/+123
* testsuite/synth: add testcase for #952Tristan Gingold2019-09-303-1/+87
* synth-oper: implement >= and <= for uns/nat. Fix #952Tristan Gingold2019-09-301-0/+6
* testsuite/synth: add testcase for #951Tristan Gingold2019-09-303-0/+87
* synth-inference: handl 'EXPR and CLK' condition. Fix #951Tristan Gingold2019-09-301-2/+17
* synth-insts: refactoring.Tristan Gingold2019-09-301-40/+32
* testsuite/synth: add testcase for #954Tristan Gingold2019-09-304-0/+46
* synth-insts: create net object for input port. FixTristan Gingold2019-09-301-3/+14
* synth: renaming and minor refactoring.Tristan Gingold2019-09-304-74/+43
* synth: minor refactoring.Tristan Gingold2019-09-301-4/+4
* synth-expr: minor factorisation.Tristan Gingold2019-09-301-25/+19
* testsuite/synth: add a test for 'to' direction.Tristan Gingold2019-09-303-1/+64
* testsuite: add test for previous commit.Tristan Gingold2019-09-301-0/+11
* vhdl-std_package: reduce cascaded error messages.Tristan Gingold2019-09-301-0/+1
* synth-decls: improve handling of subtype aliases forTristan Gingold2019-09-301-26/+42
* testsuite/synth: add testcase for #947Tristan Gingold2019-09-302-0/+32
* synth: check matching bounds for array equality. Fix #947Tristan Gingold2019-09-303-4/+56
* testsuite/synth: add testcase for #946Tristan Gingold2019-09-302-0/+34
* synth: convert subtype in alias declaration. Fix #946Tristan Gingold2019-09-301-2/+6
* testsuite/synth: add testcase for #948Tristan Gingold2019-09-303-1/+33
* synth: handle alias for is_const. Fix #948Tristan Gingold2019-09-301-2/+3
* synth: handle conversion from slice to unbounded vector.Tristan Gingold2019-09-301-0/+2
* synth: handle while-loop statement.Tristan Gingold2019-09-301-0/+39
* synth: special handling of 'const' functions.Tristan Gingold2019-09-307-16/+134
* synth: slice: avoid crash in case of incorrect slice.Tristan Gingold2019-09-301-4/+4
* synth: refactoring of alias (allow alias of anything).Tristan Gingold2019-09-307-34/+40
* testsuite/synth: add a test for previous commit (dyn slice).Tristan Gingold2019-09-303-1/+84
* synth: handle slice with index from a record.Tristan Gingold2019-09-301-5/+15
* synth: introduce type_logicTristan Gingold2019-09-296-16/+42
* testsuite/synth: add testcase for #945Tristan Gingold2019-09-283-0/+30
* synth: add support of alias of alias. Fix #945Tristan Gingold2019-09-281-0/+8
* synth: add support for mod operator.Tristan Gingold2019-09-283-24/+30
* netlists-disp_vhdl: improve disp_x_lit.Tristan Gingold2019-09-281-3/+9
* testsuite/sync: re-enable func08Tristan Gingold2019-09-281-1/+1
* synth-environment: optimize cascaded if.Tristan Gingold2019-09-281-1/+27
* netlists-disp_vhdl: handle id_edge.Tristan Gingold2019-09-281-0/+3
* testsuite/synth: add if01Tristan Gingold2019-09-283-0/+75
* testsuite/synth/func01: replace func08 by func08b (need to optimize).Tristan Gingold2019-09-283-1/+61
* synth-stmts: simple optimization for loop control logic.Tristan Gingold2019-09-281-10/+19
* synth: disp net number in netlists-dumpTristan Gingold2019-09-281-1/+13
* synth: finalize declarations and free wires.Tristan Gingold2019-09-276-21/+214
* testsuite/synth: add testcase for #944Tristan Gingold2019-09-272-0/+33
* synth: handle range attribute; handle vhdl08 array subtype.Tristan Gingold2019-09-271-19/+25
* synth-environment-debug: improve.Tristan Gingold2019-09-261-1/+2
* synth: handle alias for reshape.Tristan Gingold2019-09-261-0/+2
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-05 19:11:42 +0000