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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-26 19:42:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-26 19:42:25 +0200 |
| commit | fb30460433764b495dc05d5a1a90acb724a7706a (patch) | |
| tree | b55bd2ce3b9f441809bc3133a2d7632f8020fb13 | |
| parent | 4ddc16c4e656b5a0816b5cc35299c346a40152b7 (diff) | |
| download | ghdl-fb30460433764b495dc05d5a1a90acb724a7706a.tar.gz ghdl-fb30460433764b495dc05d5a1a90acb724a7706a.tar.bz2 ghdl-fb30460433764b495dc05d5a1a90acb724a7706a.zip | |
synth-environment-debug: improve.
| -rw-r--r-- | src/synth/synth-environment-debug.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-environment-debug.adb b/src/synth/synth-environment-debug.adb index ca7c989b8..7f378130b 100644 --- a/src/synth/synth-environment-debug.adb +++ b/src/synth/synth-environment-debug.adb @@ -29,10 +29,11 @@ package body Synth.Environment.Debug is Put ("Wire:" & Wire_Id'Image (Id)); Put_Line (" kind: " & Wire_Kind'Image (W_Rec.Kind)); Put_Line (" decl:" & Source.Syn_Src'Image (W_Rec.Decl)); - Put (" Init: "); + Put (" gate: "); Dump_Net_Name (W_Rec.Gate); New_Line; Put_Line (" cur_assign:" & Seq_Assign'Image (W_Rec.Cur_Assign)); + Put_Line (" conc_assign:" & Conc_Assign'Image(W_Rec.Final_Assign)); end Dump_Wire_Id; procedure Dump_Assign (Asgn : Seq_Assign) |