iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	fix(configure): disable -Werror by default	Xiretza	2022-05-16	5	-3/+7
\| \| \| \| \| \| \| \| \| \| \| \|	Because the build system does not have direct control over the compiler, it cannot ensure that no warnings are issued in downstream compilations. Such warnings can occur due to newer compiler versions with more sophisticated diagnostics, older compiler versions with diagnostics bugs, or simply different, untested compilers. With -Werror enabled by default, these harmless warnings result in complete compilation failures. The option remains enabled in CI to ensure upstream code quality.
*	vhdl-sem_specs: use by_name assoc for port default association	Tristan Gingold	2022-05-16	1	-1/+5
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*	ghdlcomp(common_compile_elab): add allow_undef_generic parameter	Tristan Gingold	2022-05-16	4	-4/+8
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*	elab-vhdl_debug(disp_instance_path): can also display components	Tristan Gingold	2022-05-16	2	-7/+23
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*	elab-vhdl_debug: factorize code, make Put_Dir public	Tristan Gingold	2022-05-16	2	-12/+6
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*	pyGHDL: limit pyTooling version to 1.10.0	Tristan Gingold	2022-05-15	3	-4/+4
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*	elab-vhdl_values: rename signal_index to signal_index_type	Tristan Gingold	2022-05-15	3	-5/+5
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*	pyGHDL: tentatively work-around incompatibility with pyTooling	Tristan Gingold	2022-05-15	1	-2/+2
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*	grt-readline_none.adb: do not use getline(3)	Tristan Gingold	2022-05-15	1	-19/+24
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*	elab-vhdl_values-debug: add disp_type_short	Tristan Gingold	2022-05-15	2	-8/+58
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*	elab-vhdl_debug: improve info signals	Tristan Gingold	2022-05-15	1	-20/+19
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*	elab-debugger: add append_info_menu, to_num	Tristan Gingold	2022-05-15	2	-5/+50
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*	trans_analyzes: add support for all processes	Tristan Gingold	2022-05-15	1	-85/+116
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*	elab-vhdl_debug(disp_instance_path): show top-level unit	Tristan Gingold	2022-05-15	1	-13/+5
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*	elab-debugger: add append_menu_command	Tristan Gingold	2022-05-15	2	-7/+29
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*	synth: elab-debugger__on.adb is now elab-debugger.adb	Tristan Gingold	2022-05-15	2	-975/+929
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*	configure: generate grt-readline.ads	Tristan Gingold	2022-05-15	3	-2/+9
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*	grt: add grt-readline_gnu and grt-readline_none	Tristan Gingold	2022-05-15	5	-14/+105
\| \| \| \|	grt-readline is now a renaming of grt-readline_gnut
*	grt: simplifies grt-readline, adjust casing	Tristan Gingold	2022-05-15	5	-17/+13
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*	elab-vhdl_stmts: change parent of generate_body for for-generate	Tristan Gingold	2022-05-14	1	-1/+1
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*	ghdlsimul: add and improve debugger	Tristan Gingold	2022-05-14	6	-26/+471
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*	vhdl-errors(disp_node): change message for generate body	Tristan Gingold	2022-05-14	1	-1/+1
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*	elab-vhdl_context: add get_instance_parent	Tristan Gingold	2022-05-14	2	-0/+10
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*	GCC 12 compatibility (#2057)	Unai Martinez-Corral	2022-05-14	7	-8/+4
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\| *	fix: avoid "pragma Unreferenced given" warnings with GCC 12	Xiretza	2022-05-14	3	-3/+3
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\| *	fix: avoid "unnecessary with of ancestor [-gnatwr]" with GCC 12	Xiretza	2022-05-14	4	-5/+1
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*	scripts/vendors/compile-osvvm.sh: update Files. Fix #1900	umarcor	2022-05-14	1	-4/+7
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*	synth: implement file_open with status	Tristan Gingold	2022-05-12	3	-0/+69
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*	vhdl-canon: export extract_waveform_sensitivity	Tristan Gingold	2022-05-12	1	-2/+5
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*	trans_analyzes.adb: reindent	Tristan Gingold	2022-05-12	1	-3/+2
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*	synth-vhdl_stmts: export synth_target	Tristan Gingold	2022-05-12	2	-35/+39
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*	synth-vhdl_expr: add an hook to get the value of a signal	Tristan Gingold	2022-05-12	2	-0/+9
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*	elab-vhdl_debug: also disp declarations in instances	Tristan Gingold	2022-05-12	1	-4/+1
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*	elab-memtype.adb: identation	Tristan Gingold	2022-05-12	1	-1/+1
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*	ghdlsimul: add option -t to trace statements	Tristan Gingold	2022-05-12	1	-0/+2
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*	ghdllocal.adb: move pragma suppress. Fix #2056	Tristan Gingold	2022-05-12	1	-1/+1
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*	ghdlsimul: now based on synth elab	Tristan Gingold	2022-05-11	3	-102/+119
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*	synth: handle text file write	Tristan Gingold	2022-05-11	3	-0/+93
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*	synth: add a flag to force creation of variables	Tristan Gingold	2022-05-11	5	-9/+21
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*	ghdlsynth.adb: remove -E experimental command	Tristan Gingold	2022-05-10	1	-145/+42
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*	synth: add current_stmt, minor rework	Tristan Gingold	2022-05-09	4	-61/+99
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*	testsuite/synth: add a test for #2053	Tristan Gingold	2022-05-07	3	-0/+127
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*	synth-vhdl_insts: handle interfaces of type interface type. Fix #2053	Tristan Gingold	2022-05-07	1	-1/+12
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*	testsuite/gna: add a test for #2051	Tristan Gingold	2022-05-07	4	-0/+2375
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*	vhdl: consider fully static record aggregates. Fix #2051	Tristan Gingold	2022-05-07	4	-26/+83
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*	ortho/debug: handle aggregates of record-subtype	Tristan Gingold	2022-05-07	3	-7/+25
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*	elab-vhdl_context: introduce signal_index	Tristan Gingold	2022-05-06	3	-3/+12
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*	testsuite/gna: add a test for #2050	Tristan Gingold	2022-05-06	2	-0/+25
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*	vhdl-sem.adb(are_trees_equal): handle selected element. Fix #2050	Tristan Gingold	2022-05-06	1	-0/+4
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*	testsuite/gna: add a test for #2048	Tristan Gingold	2022-05-03	2	-0/+4
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