testsuite/synth: add a test for #2053

3 files changed, 127 insertions, 0 deletions

diff --git a/testsuite/synth/issue2053/generic_fifo_fwft.vhdl b/testsuite/synth/issue2053/generic_fifo_fwft.vhdl
new file mode 100644
index 000000000..c226aade0
--- /dev/null
+++ b/testsuite/synth/issue2053/generic_fifo_fwft.vhdl
@@ -0,0 +1,68 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity generic_fifo_fwft is 
+  generic (
+    type stream_t;
+    size : integer := 256;
+    async_reset : boolean := false
+  );
+  port (
+         clk     : in  std_logic;
+         rst     : in  std_logic;
+         datain  : in  stream_t;
+         dataout : out stream_t;
+         empty   : out std_logic;
+         full    : out std_logic;
+         wr      : in  std_logic;
+         rd      : in  std_logic
+       );
+end;
+architecture a_generic_fifo_fwft of generic_fifo_fwft is 
+  type memory_t is array(size-1 downto 0) of stream_t;
+  signal wrptr : integer range 0 to size - 1;
+  signal rdptr : integer range 0 to size - 1;
+  signal mem : memory_t;
+  signal inverted : boolean;
+begin
+
+  empty <= '1' when (rdptr = wrptr) and not inverted else '0';
+  full  <= '1' when (rdptr = wrptr) and     inverted else '0';
+
+  dataout <= mem(rdptr);
+
+  process (all) is
+  begin
+    if rising_edge(clk) then
+      if wr and not full then
+        mem(wrptr) <= datain;
+        wrptr <= wrptr + 1;
+      end if;
+      if rd and not empty then
+        rdptr <= rdptr + 1;
+      end if;
+      if wr and rd then
+        null;
+      elsif wr and not full then
+        inverted <= not inverted when wrptr + 1 mod size < wrptr;
+      elsif rd and not empty then
+        inverted <= not inverted when rdptr + 1 mod size < rdptr;
+      end if;
+      if not async_reset then
+        if rst then
+          inverted <= false;
+          rdptr <= 0;
+          wrptr <= 0;
+        end if;
+      end if;
+    end if;
+    if async_reset then
+      if rst then
+        inverted <= false;
+        rdptr <= 0;
+        wrptr <= 0;
+      end if;
+    end if;
+  end process;
+end;
diff --git a/testsuite/synth/issue2053/generic_fifo_fwft_inst.vhdl b/testsuite/synth/issue2053/generic_fifo_fwft_inst.vhdl
new file mode 100644
index 000000000..b2d18ca3e
--- /dev/null
+++ b/testsuite/synth/issue2053/generic_fifo_fwft_inst.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+--use work.utils.all;
+
+entity generic_fifo_fwft_inst is 
+  port (
+         clk     : in  std_logic;
+         rst     : in  std_logic;
+         datain  : in  std_logic_vector(7 downto 0);
+         dataout : out std_logic_vector(7 downto 0);
+         empty   : out std_logic;
+         full    : out std_logic;
+         wr      : in  std_logic;
+         rd      : in  std_logic
+       );
+end;
+
+architecture a_generic_fifo_fwft_inst of generic_fifo_fwft_inst is 
+  type mystream_t is record
+    x : std_logic_vector(3 downto 0);
+    y : integer range 0 to 2**4-1;
+  end record;
+  signal imin  : mystream_t;
+  signal imout : mystream_t;
+begin
+
+  dataout <= imin.x & std_logic_vector(to_unsigned(imin.y, 4));
+  imin.x <= datain(7 downto 4);
+  imin.y <= to_integer(unsigned(datain(3 downto 0)));
+
+
+fifo: entity work.generic_fifo_fwft 
+  generic map (
+    stream_t    => mystream_t,
+    size        => 256,
+    async_reset => false
+  )
+  port map (
+         clk     => clk,
+         rst     => rst,
+         datain  => imin,
+         dataout => imout,
+         empty   => empty,
+         full    => full,
+         wr      => wr,
+         rd      => rd
+       );
+end architecture;
diff --git a/testsuite/synth/issue2053/testsuite.sh b/testsuite/synth/issue2053/testsuite.sh
new file mode 100755
index 000000000..9d3020a7f
--- /dev/null
+++ b/testsuite/synth/issue2053/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth generic_fifo_fwft.vhdl generic_fifo_fwft_inst.vhdl -e > syn_generic_fifo_fwft_inst
+
+echo "Test successful"