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* vhdl-nodes: renaming.Tristan Gingold2022-07-2123-143/+145
* elab-vhdl_decls: elaborate implicit signalsTristan Gingold2022-07-211-2/+23
* Makefile.in: allow build of ghdl_mcode with sundials enabledTristan Gingold2022-07-212-1/+26
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-202-11/+23
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* grt: add analog_solver (work in progress)Tristan Gingold2022-07-204-9/+197
* grt: add real now variable.Tristan Gingold2022-07-204-0/+19
* ghdlsimul: simplify elaboration circuiteryTristan Gingold2022-07-201-13/+0
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* configure: add --with-sundials (preliminary work)Tristan Gingold2022-07-204-1/+56
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-204-2/+10
* testsuite/gna: add a test for #2134Tristan Gingold2022-07-163-0/+61
* vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134Tristan Gingold2022-07-161-0/+2
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-167-2/+26
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
* grt-types: add Mode_AboveTristan Gingold2022-07-164-7/+15
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-165-22/+38
* vhdl-cannon: add Canon_Extract_Sensitivity_Break_StatementTristan Gingold2022-07-162-1/+16
* netlists-inference: add (disabled) code to add a latchTristan Gingold2022-07-161-26/+103
* testsuite/synth: add latch01Tristan Gingold2022-07-143-0/+57
* testsuite/synth: use standard functions for issue2125Tristan Gingold2022-07-141-8/+2
* synth: Display dlatchTristan Gingold2022-07-143-2/+9
* Makefile.in: add dependency for local install of synth_gates.hTristan Gingold2022-07-141-1/+1
* netlists: add d-latchTristan Gingold2022-07-123-2/+38
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* testsuite/synth: add a test for #2125Tristan Gingold2022-07-116-0/+152
* testsuite/synth/dff02: do not run dff06 (creates a latch)Tristan Gingold2022-07-111-1/+2
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
* testsuite/synth: add a test for #2113Tristan Gingold2022-07-082-0/+66
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* testsuite/synth: add a test for #2129Tristan Gingold2022-07-062-0/+32
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* testsuite/gna: adjust previous commitTristan Gingold2022-07-061-2/+10
* testsuite/gna: add more tests for #2116Tristan Gingold2022-07-063-0/+18
* Fix CI failure on macosx (llvm) (#2128)tgingold2022-07-061-4/+2
* Merge pull request #2127 from C-Elegans/to_ux01_unhandled_functiontgingold2022-07-053-1/+31
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| * Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-053-1/+31
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* ci/Test: typoumarcor2022-07-051-1/+1
* Test.yml: list brew package on macosTristan Gingold2022-07-051-4/+2
* testsuite/synth: add a test for #2124Tristan Gingold2022-07-054-0/+81
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* Test.yml: add more debug commands for macosTristan Gingold2022-07-041-1/+1
* Test.yml: fix syntaxTristan Gingold2022-07-041-4/+5
* Test.yml: untabifyTristan Gingold2022-07-041-3/+3
* github/workflows: add log for llvm on macosTristan Gingold2022-07-041-0/+3
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