diff options
Diffstat (limited to 'testsuite')
17 files changed, 190 insertions, 47 deletions
diff --git a/testsuite/pyunit/dom/StopWatch.py b/testsuite/pyunit/dom/StopWatch.py index 37b8293de..6301eb1df 100644 --- a/testsuite/pyunit/dom/StopWatch.py +++ b/testsuite/pyunit/dom/StopWatch.py @@ -34,7 +34,7 @@ from pathlib import Path from unittest import TestCase from pyGHDL.dom.NonStandard import Design, Document - +from pyGHDL.dom.formatting.prettyprint import PrettyPrint if __name__ == "__main__": print("ERROR: you called a testcase declaration file as an executable module.") @@ -47,51 +47,59 @@ class Designs(TestCase): _sourceDirectory: Path = _root / "dom/examples/StopWatch" _packageFiles = ( - Path("Utilities.pkg.vhdl"), - Path("StopWatch.pkg.vhdl"), + ("lib_Utilities", Path("Utilities.pkg.vhdl")), + ("lib_Utilities", Path("Utilities.ctx.vhdl")), + ("lib_StopWatch", Path("StopWatch.pkg.vhdl")), + ("lib_StopWatch", Path("StopWatch.ctx.vhdl")), ) _encoderFiles = _packageFiles + ( - Path("seg7_Encoder.vhdl"), - Path("toplevel.Encoder.vhdl"), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("toplevel.Encoder.vhdl")), ) _displayFiles = _packageFiles + ( - Path("Counter.vhdl"), - Path("seg7_Encoder.vhdl"), - Path("seg7_Display.vhdl"), - Path("toplevel.Display.vhdl"), + ("lib_StopWatch", Path("Counter.vhdl")), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")), + ("lib_StopWatch", Path("toplevel.Display.vhdl")), ) _stopwatchFiles = _packageFiles + ( - Path("Counter.vhdl"), - Path("seg7_Encoder.vhdl"), - Path("seg7_Display.vhdl"), - Path("StopWatch.vhdl"), - Path("Debouncer.vhdl"), - Path("toplevel.StopWatch.vhdl"), + ("lib_Utilities", Path("Counter.vhdl")), + ("lib_StopWatch", Path("seg7_Encoder.vhdl")), + ("lib_StopWatch", Path("seg7_Display.vhdl")), + ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")), + ("lib_StopWatch", Path("StopWatch.vhdl")), + ("lib_Utilities", Path("sync_Bits.vhdl")), + ("lib_Utilities", Path("Debouncer.vhdl")), + ("lib_StopWatch", Path("toplevel.StopWatch.vhdl")), ) class Display(Designs): def test_Encoder(self): design = Design() - for file in self._encoderFiles: + for lib, file in self._encoderFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._encoderFiles), len(design.Documents)) def test_Display(self): design = Design() - for file in self._displayFiles: + for lib, file in self._displayFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._displayFiles), len(design.Documents)) def test_StopWatch(self): design = Design() - for file in self._stopwatchFiles: + for lib, file in self._stopwatchFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) - design.Documents.append(document) + design.AddDocument(document, library) self.assertEqual(len(self._stopwatchFiles), len(design.Documents)) @@ -101,9 +109,16 @@ class CompileOrder(Designs): design = Design() design.LoadStdLibrary() design.LoadIEEELibrary() - library = design.GetLibrary("lib_StopWatch") - for file in self._encoderFiles: + for lib, file in self._encoderFiles: + library = design.GetLibrary(lib) document = Document(self._sourceDirectory / file) design.AddDocument(document, library) design.Analyze() + + PP = PrettyPrint() + buffer = [] + buffer.append("Design:") + for line in PP.formatDesign(design, 1): + buffer.append(line) + print("\n".join(buffer)) diff --git a/testsuite/pyunit/dom/VHDLLibraries.py b/testsuite/pyunit/dom/VHDLLibraries.py index 9de39b81b..c8a39ed23 100644 --- a/testsuite/pyunit/dom/VHDLLibraries.py +++ b/testsuite/pyunit/dom/VHDLLibraries.py @@ -85,7 +85,7 @@ def test_Synopsys(file): @mark.xfail(reason="Needs further investigations.") @mark.parametrize("file", [str(f.relative_to(_VITAL_ROOT)) for f in _VITAL_ROOT.glob("*.vhdl")]) -def test_Synopsys(file): +def test_Vital(file): filePath = _VITAL_ROOT / file lib = design.GetLibrary("vital") diff --git a/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl index 3ef284b98..b26a0fa09 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Counter.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +use work.Utilities_pkg.all; entity Counter is diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl index 18207c7f1..ef1474164 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +use work.Utilities_pkg.all; entity Debouncer is @@ -15,7 +15,8 @@ entity Debouncer is CLOCK_PERIOD : time := 10 ns; DEBOUNCE_TIME : time := 3 ms; - BITS : positive + BITS : positive; + INPUT_SYNC : boolean := true ); port ( Clock : in std_logic; @@ -29,12 +30,27 @@ architecture rtl of Debouncer is constant DEBOUNCE_COUNTER_MAX : positive := DEBOUNCE_TIME / (CLOCK_PERIOD* ite(IS_SIMULATION, 20, 1)); constant DEBOUNCE_COUNTER_BITS : positive := log2(DEBOUNCE_COUNTER_MAX); + signal Input_sync : Input'subtype; begin assert false report "CLOCK_PERIOD: " & time'image(CLOCK_PERIOD); assert false report "DEBOUNCE_TIME: " & time'image(DEBOUNCE_TIME); --assert false report "DEBOUNCE_COUNTER_MAX: " & to_string(10 ns); --assert false report "INTEGER'high: " & integer'image(integer'high); + genSync: if INPUT_SYNC generate + sync: entity work.sync_Bits + generic map ( + BITS => BITS + ) + port map ( + Clock => Clock, + Input => Input, + Output => Input_sync + ); + else generate + Input_sync <= Input; + end generate; + genBits: for i in Input'range generate signal DebounceCounter : signed(DEBOUNCE_COUNTER_BITS downto 0) := to_signed(DEBOUNCE_COUNTER_MAX - 3, DEBOUNCE_COUNTER_BITS + 1); begin diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl new file mode 100644 index 000000000..dc89d5b3b --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.ctx.vhdl @@ -0,0 +1,11 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- undocumented +-- +context StopWatch_ctx is + library lib_Utilities; + context lib_Utilities.Utilities_ctx; + + use work.StopWatch_pkg.all; +end context; diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl index 3bcafdd6d..f67f99c72 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; - +-- Package with stop watch specific types. package StopWatch_pkg is subtype T_BCD is unsigned(3 downto 0); type T_BCD_Vector is array(natural range <>) of T_BCD; @@ -18,4 +18,16 @@ package StopWatch_pkg is end record; type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION; + + -- Encoder that translates from 4-bit binary (BCD) to 7-segment code. + -- + -- In addition, an optional dot input is supported. + component seg7_Encoder is + port ( + BCDValue : in T_BCD; + Dot : in std_logic := '0'; + + Seg7Code : out std_logic_vector(7 downto 0) + ); + end component; end package; diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl index c7c9068ab..3d73fa0fa 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl new file mode 100644 index 000000000..050682098 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.ctx.vhdl @@ -0,0 +1,12 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- undocumented +-- +context Utilities_ctx is + library IEEE; + use IEEE.std_logic_1164.all, + IEEE.numeric_std.all; + + use work.Utilities_pkg.all; +end context; diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl index 8daf39614..6231261c0 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl @@ -8,7 +8,8 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -package Utilities is +-- Useful utility functions and types. +package Utilities_pkg is type freq is range integer'low to integer'high units Hz; kHz = 1000 Hz; @@ -29,10 +30,25 @@ package Utilities is function to_index(value : unsigned; max : positive) return natural; function to_index(value : natural; max : positive) return natural; + + component Debouncer is + generic ( + CLOCK_PERIOD : time := 10 ns; + DEBOUNCE_TIME : time := 3 ms; + + BITS : positive + ); + port ( + Clock : in std_logic; + + Input : in std_logic_vector(BITS - 1 downto 0); + Output : out std_logic_vector(BITS - 1 downto 0) := (others => '0') + ); + end component; end package; -package body Utilities is +package body Utilities_pkg is function simulation return boolean is variable result : boolean := FALSE; begin diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl new file mode 100644 index 000000000..63d0c5e60 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl @@ -0,0 +1,16 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic counter module used in the StopWatch example. +-- +context work.StopWatch_ctx; + + +-- Encoder that translates from 4-bit binary (BCD) to 7-segment code. +configuration seg7_Display_cfg of seg7_Display is + for rtl + for enc : seg7_Encoder + use entity work.seg7_Encoder(rtl); + end for; + end for; +end configuration; diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl index c3771ba68..da21075cf 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; @@ -77,7 +79,7 @@ begin Dot <= DotValues(to_index(Digit_Select, DotValues'high)); -- 7-segment encoder - enc: entity work.seg7_Encoder + enc: configuration seg7_Encoder port map ( BCDValue => Digit, Dot => Dot, diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl index e4c731ff9..88074c884 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Encoder.vhdl @@ -3,14 +3,10 @@ -- -- A generic counter module used in the StopWatch example. -- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -use work.Utilities.all; -use work.StopWatch_pkg.all; +context work.StopWatch_ctx; +-- Encoder that translates from 4-bit binary (BCD) to 7-segment code. entity seg7_Encoder is port ( BCDValue : in T_BCD; diff --git a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl new file mode 100644 index 000000000..499305ec7 --- /dev/null +++ b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl @@ -0,0 +1,37 @@ +-- Author: Patrick Lehmann +-- License: MIT +-- +-- A generic multi-FF synchronizer. +-- +library ieee; +use ieee.std_logic_1164.all; + + +-- Multi-stage FF synchronizer +entity sync_Bits is + generic ( + BITS : positive := 1; + STAGES : positive range 2 to 5 := 3 + ); + port ( + Clock : in std_logic; + + Input : in std_logic_vector(BITS - 1 downto 0); + output : in std_logic_vector(BITS - 1 downto 0) + ); +end entity; + + +architecture rtl of sync_Bits is + +begin + gen : for i in Input'range generate + signal meta : std_logic := '0'; + signal ffs : std_logic_vector(STAGES - 1 downto 1) := (others => '0'); + begin + meta <= Input(i) when rising_edge(Clock); + ffs <= (ffs(ffs'left downto 1) & meta) when rising_edge(Clock); + + Output(i) <= ffs(ffs'left); + end generate; +end architecture; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl index 67228a5ac..648ab81e4 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Display.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl index 7775a6eb6..17f7c6b19 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.Encoder.vhdl @@ -7,10 +7,13 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; +-- Toplevel module to demonstrate the translation of 4 slide-switches to 1 digit 7-segment display. entity toplevel is port ( NexysA7_GPIO_Switch : in std_logic_vector(3 downto 0); diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl index a334475c4..87cd75829 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.tb.vhdl @@ -7,9 +7,10 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lib_StopWatch; -use lib_StopWatch.Utilities.all; -use lib_StopWatch.StopWatch_pkg.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + +use work.StopWatch_pkg.all; entity toplevel_tb is diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl index 1c8547446..08046e2cc 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl @@ -7,7 +7,9 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities.all; +library lib_Utilities; +use lib_Utilities.Utilities_pkg.all; + use work.StopWatch_pkg.all; @@ -57,7 +59,7 @@ begin Board_Reset <= not NexysA7_GPIO_Button_Reset_n; -- Debounce input signals - deb: entity work.Debouncer + deb: component Debouncer generic map ( CLOCK_PERIOD => CLOCK_PERIOD, BITS => 2 @@ -98,7 +100,7 @@ begin ); -- 7-segment display - display: entity work.seg7_Display + display: configuration seg7_Display_cfg generic map ( CLOCK_PERIOD => CLOCK_PERIOD, DIGITS => Digits'length |