diff options
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1628/test.vhdl | 17 | ||||
-rw-r--r-- | testsuite/synth/issue1628/test2.vhdl | 14 | ||||
-rwxr-xr-x | testsuite/synth/issue1628/testsuite.sh | 9 |
3 files changed, 40 insertions, 0 deletions
diff --git a/testsuite/synth/issue1628/test.vhdl b/testsuite/synth/issue1628/test.vhdl new file mode 100644 index 000000000..c7de976c1 --- /dev/null +++ b/testsuite/synth/issue1628/test.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std_unsigned.all; + +entity test is +end entity test; + +architecture synthesis of test is + + signal a : std_logic_vector(3 downto 0); + +begin + + a <= to_stdlogicvector(10, 4); + +end architecture synthesis; + diff --git a/testsuite/synth/issue1628/test2.vhdl b/testsuite/synth/issue1628/test2.vhdl new file mode 100644 index 000000000..93f2d094a --- /dev/null +++ b/testsuite/synth/issue1628/test2.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std_unsigned.all; + +entity test2 is + port ( + a : out std_logic_vector(3 downto 0)); +end entity test2; + +architecture synthesis of test2 is +begin + a <= to_stdlogicvector(10, 4); +end architecture synthesis; + diff --git a/testsuite/synth/issue1628/testsuite.sh b/testsuite/synth/issue1628/testsuite.sh new file mode 100755 index 000000000..df2069561 --- /dev/null +++ b/testsuite/synth/issue1628/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only test +synth_only test2 + +echo "Test successful" |