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Diffstat (limited to 'testsuite/synth/psl02/verif3.vhdl')
-rw-r--r-- | testsuite/synth/psl02/verif3.vhdl | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/verif3.vhdl b/testsuite/synth/psl02/verif3.vhdl new file mode 100644 index 000000000..c1b262177 --- /dev/null +++ b/testsuite/synth/psl02/verif3.vhdl @@ -0,0 +1,6 @@ +vunit verif2 (assert2(behav)) +{ + default clock is rising_edge(clk); + assume always val < 10; + assert always val /= 5 abort rst; +} |