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-rw-r--r--testsuite/synth/psl02/verif3.vhdl6
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diff --git a/testsuite/synth/psl02/verif3.vhdl b/testsuite/synth/psl02/verif3.vhdl
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+++ b/testsuite/synth/psl02/verif3.vhdl
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+vunit verif2 (assert2(behav))
+{
+ default clock is rising_edge(clk);
+ assume always val < 10;
+ assert always val /= 5 abort rst;
+}