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-rw-r--r--testsuite/synth/psl01/assert1.vhdl2
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/psl01/assert1.vhdl b/testsuite/synth/psl01/assert1.vhdl
index 13e44a1e8..717b4d0f9 100644
--- a/testsuite/synth/psl01/assert1.vhdl
+++ b/testsuite/synth/psl01/assert1.vhdl
@@ -23,5 +23,5 @@ begin
cnt <= val;
--psl default clock is rising_edge(clk);
- --psl assert always val /= 5 or rst = '1';
+ --psl assert always val /= 5 abort rst;
end behav;