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-rw-r--r--testsuite/synth/match01/match02.vhdl12
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diff --git a/testsuite/synth/match01/match02.vhdl b/testsuite/synth/match01/match02.vhdl
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+++ b/testsuite/synth/match01/match02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity match02 is
+ port (a : in std_logic_vector (3 downto 0);
+ z : out std_logic);
+end match02;
+
+architecture behav of match02 is
+begin
+ z <= a ?/= "1--0";
+end behav;