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-rw-r--r--testsuite/synth/issue34/repro_nat.vhdl42
1 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/issue34/repro_nat.vhdl b/testsuite/synth/issue34/repro_nat.vhdl
new file mode 100644
index 000000000..328c11781
--- /dev/null
+++ b/testsuite/synth/issue34/repro_nat.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub_nat is
+ port (
+ clk : in std_logic;
+ a : in natural;
+ b : out natural
+ );
+end sub_nat;
+
+architecture rtl of sub_nat is
+begin
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ b <= a;
+ end if;
+ end process;
+end rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro_nat is
+ port (
+ clk : in std_logic;
+ a : in natural;
+ b : out natural
+ );
+end repro_nat;
+
+architecture rtl of repro_nat is
+begin
+ i_sub_nat : entity work.sub_nat
+ port map (
+ clk => clk,
+ a => a,
+ b => b
+ );
+end rtl;